AM79C875KI AMD (ADVANCED MICRO DEVICES), AM79C875KI Datasheet

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AM79C875KI

Manufacturer Part Number
AM79C875KI
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of AM79C875KI

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Am79C875
NetPHY™ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver
DISTINCTIVE CHARACTERISTICS
■ Four 10/100BASE-TX Ethernet PHY transceivers
■ Supports RMII (Reduced MII) interface
■ 125 meter (m) MLT-3 and Baseline Wander
■ Low power consumption
■ Power management modes:
■ Single 3.3 V power supply with 5 V I/O tolerance
■ Patent-pending DC restoration technique
■ Full and half-duplex operation with full-featured
■ Next Page register support
GENERAL DESCRIPTION
The NetPHY™ 4LP device is a highly integrated, low
power 10BASE-T/100BASE-TX/FX Quad Ethernet
transceiver. The NetPHY™ 4LP device includes
integrated RMII, ENDECs, Scrambler/Descrambler,
and full-featured Auto-Negotiation with support for Par-
allel Detection and Next Page. Port 3 can be config-
ured as a 100BASE-FX transmitter to output an NRZI
PECL level signal. Each receiver has an adaptive
equalizer/DC restoration circuit for accurate clock/data
recovery on the 100BASE-TX signal at different cable
lengths and can perform to 125 m and beyond.
The NetPHY™ 4LP device operates on a 3.3 V supply
and offers 5 V I/O tolerance for mixed signal designs.
Power consumption is 1.3 W typical for the device, or
0.3 W per port using 1:1 magnetics. The NetPHY™
4LP device can use 1.25:1 magnetics, which de-
creases transmit power consumption and reduces de-
vice power consumption to 1.2 W typical.
The NetPHY™ 4LP device offers an optimized pinout
for network applications. RMII pins can be routed di-
operation
— 1.3 Watt (W) typical (1:1 magnetics)
— 1.2 W typical (1.25:1 magnetics)
— Selectable 1:1 or 1.25:1 transmit transformer
— Unplugged - approximately 100 mW per port
— Power Down - approximately 3 mW per port
reduces baseline wander susceptibility
Auto-Negotiation function
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A
■ Automatic Polarity Detection during Auto-
■ Unique scramble seed per port reduces EMI in
■ One port supports 100BASE-FX function
■ Supports Inter Packet Gap as low as 40 ns for
■ No external filters or chokes required
■ Compliant with IEEE 802.3 standards for
■ Built-in loopback and test modes
■ Small 14 x 20 mm 100-pin PQR package
■ Small package allows side-by-side PHY layout
■ Support for Industrial Temperature
rectly to the MAC and TX/RX media pins are routed di-
rectly to the magnetics. Direct routing of high speed
traces is imperative for project system design and EMI
noise
The NetPHY™ 4LP device’s on-chip input filtering and
output waveshaping eliminates the need of external hy-
brid filters for media connection. Integrated LED logic
allows three LEDs per port to be driven directly. These
features greatly simplify the design of a 100BASE-X re-
peater/switch board, thus requiring minimum external
components.
For ease of system and chip setup and testing, the Net-
PHY™ 4LP device offers loopback and various ad-
vanced testing and monitoring capabilities.
The NetPHY™ 4LP device is available in the Commer-
cial (0°C to 70°C) or Industrial (-40°C to +85°C) tem-
perature ranges. The Industrial temperature range is
well suited to environment such as enclosures with re-
stricted air flow or outdoor equipment.
S H E E T
Negotiation and 10BASE-T signal reception
switch and repeater applications
high throughput applications
100BASE-TX, 100BASE-FX, and 10BASE-T
— Fits neatly behind quad magnetics
— Saves board space over larger 208 PQFP
(-40°C to +85°C)
packages
reduction.
Publication# 22236 Rev: I Amendment/0
Issue Date: September 2005

Related parts for AM79C875KI

AM79C875KI Summary of contents

Page 1

... The NetPHY™ 4LP device operates on a 3.3 V supply and offers 5 V I/O tolerance for mixed signal designs. Power consumption is 1.3 W typical for the device, or 0.3 W per port using 1:1 magnetics. The NetPHY™ ...

Page 2

... BLOCK DIAGRAM (PER PORT) Carrier Detect RMII Data Interface Interface MAC MDC/MDIO MII Serial Management Interface and Registers PHYAD[4:0] 2 PMA TP_PMD PCS Framer Clock Recovery Link Monitor Stream Cipher 4B/5B Signal Detect 25 MHz 10TX 10BASE-T 10RX Control/Status 20 MHz PLL Clk Generator ...

Page 3

CONNECTION DIAGRAM Am79C875 22236G-2 3 ...

Page 4

LOGIC SYMBOL 4 Am79C875 ...

Page 5

... PACKAGE TYPE K = 100-Pin Plastic Quad Flat Pack (PQR100) SPEED OPTION Not Applicable DEVICE NUMBER/DESCRIPTION AM79C875 NetPHY™ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver KC Valid Combinations list configurations planned to be sup- KI ported in volume for this device. Consult the local AMD sales ...

Page 6

... RELATED AMD PRODUCTS Part No. Description Integrated Controllers Am97C973B/975B PCnet-FAST™ III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY Am79C976 PCnet-PRO™ 10/100 Mbps PCI Ethernet Controller Am79C978A PCnet-Home™ Single-Chip 1/10 Mbps PCI Home Networking Controller Physical Layer Devices (Single-Port) Am79C874 NetPHY™ ...

Page 7

... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 100BASE-X Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 10BASE-T Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Auto-Negotiation and Miscellaneous Functions .21 Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Power Savings Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 LED Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PHY Control and Management Block (PCM Block .23 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 DC CHARACTERISTICS .34 Power Supply Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 SWITCHING CHARACTERISTICS ...

Page 8

... LIST OF TABLES Table 1. Code-Group Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 2. LED Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 3. Clause 22 Management Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 4. PHY Address Setting Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 5. NetPHY™ 4LP MII Management Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 6. Legend for Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 7. MII Management Control Register (Register .26 Table 8. MII Management Status Register (Register .27 Table 9 ...

Page 9

... CRS_DV[3] 73 CGND CGND 74 TXD[1]_[1] TXD[3]_[1] 75 TXD[1]_[0] Am79C875 Pin No. Pin Name 76 TX_EN[1] 77 CVDD 78 RXD[0]_[1] 79 RXD[0]_[0] 80 OVDD 81 RX_ER[0] 82 CRS_DV[0]/ 83 CGND 84 TXD[0]_[1] 85 TXD[0]_[0] 86 TX_EN[0] 87 OGND LEDDPX[1]/ 88 PHYAD[4] LEDACT_LINK[1]/ 89 PHYAD[3] LEDSPD[1]/ 90 PHYAD[2] 91 LEDDPX[0]/FX_DIS 92 LEDACT_LINK[0] 93 LEDSPD[0]/TP1_1 94 INTR 95 RST 96 GAGND 97 IBREF 98 GAVDD 99 GAVDD 100 AVDD 9 ...

Page 10

... PHYAD of each port (in binary notation) is 00000, 00001, 00010, 00011 re- spectively. If the pin is LOW at power-up and the upper- 3 bits are set to 000, the PHYAD of each port is 00001, 00010, 00011, and 00100, respectively. This allows a method of avoiding setting an address to 00000, which could cause problems with some MACs ...

Page 11

... Port [1] Speed LED LED is output low when operating in 100BASE-X modes and high when operating in 10BASE-T modes. PHY Address[2]. This is the third MSB and one of three MSB’s for MII management PHY address. To set this pin, use pull-up or pull-down resistors in the range of 1 KΩ ...

Page 12

FORCE100 has no effect on operation. ...

Page 13

... CRS_DV synchronous to the cycle of REF_CLK, which presents the first di-bit of a nibble onto RXD[1:0] (i.e., CRS_DV is deasserted only on nibble bound- aries). If the PHY has additional bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, the PHY asserts CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble ...

Page 14

... RXD[1:0]=01). RXD[1: Mbps Mode Following assertion of CRS_DV, RXD[1:0] shall be “00” until the 10BASE-T PHY has recovered clock and is able to decode the receive data. Once valid receive data is available from the 10BASE-T PHY, RXD[1:0] takes on the recovered data values (i.e., starting with “ ...

Page 15

... TXD[1:0] Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] is ac- cepted for transmission by the PHY. TXD[1:0] is ignored by the PHY while TX_EN is deasserted. TXD[1:0] in 100 Mbps Mode TXD[1:0] provides valid data for each REF_CLK period while TX_EN is asserted. Refer to Figure 3. ...

Page 16

... The resulting signal has fewer repetitive data patterns. After reset, the scrambler seed in each port will be set to the PHY address value to help improve the EMI performance of the device. The scrambled data stream is descrambled, at the re- ceiver, by adding it to the output of another random generator. The receiver’ ...

Page 17

... V In 100BASE-FX mode, the external fiber-optic receiver performs the signal energy detection function and com- municates this information directly to the NetPHY™ 4LP device through SDI± pins. In 10BASE-T mode, a link-pulse detection circuit will constantly monitor the RX± pins for the presence of valid link pulses ...

Page 18

... Twisted Pair Interface Status Data The NetPHY™ 4LP transceiver will power up in the Link Fail state. The Auto-Negotiation algorithm will apply to allow it to enter the Link Pass state. In the Link Pass state, receive activity which passes the pulse width/amplitude requirements of the RX± ...

Page 19

... Refer to Figure 7. Adaptive Equalizer The NetPHY™ 4LP device is designed for the maxi- mum of 140 meter UTP-5 cable. A 140-meter UTP-5 cable attenuates the signal 100 MHz which far exceed the cable plant attenuation (24-26 dB) de- fined by TP-PMD ...

Page 20

... Clock/Data Recovery The equalized MLT-3 signal is converted into NRZI for- mat. The NetPHY™ 4LP device uses an analog phase locked loop (APLL) to extract clock information of the incoming NRZI data which is used to re-time the data stream and set data boundaries. The receive clocks are locked to the incoming data streams ...

Page 21

... Auto- Negotiation algorithm. In the case that a 100BASE-TX only device is connected to the remote end, the Net- PHY™ 4LP device will see scrambled idle symbols and establish a 100BASE-TX only connection. If NLPs are seen, the NetPHY™ 4LP device will establish a 10BASE-T connection ...

Page 22

... Auto-Negotiation disabled. Typical power becomes 100 mW per port. Power Down Most of the NetPHY™ 4LP device can be disabled via the Power Down bit in Register 0, bit 11. Setting this bit on Register 0 of any port will power down the respec- tive port with the exception of the MDIO/MDC manage- ment circuitry ...

Page 23

... PHYADs to be shifted by 1. The PHYAD_ST pin enables this mechanism. If the pin is LOW at power-up, the PHYADs are incremented set the PHYAD pins, use pull-up or pull-down resis- tors in the range of 1 KΩ to 4.7 KΩ. If PHYAD is set to 000, the address of each port is as follows: Port 0 Port 1 Port 2 ...

Page 24

... Start Opcode PHY Address (Write) 16h, Port 2 Figure 9. PHY Management Read and Write Operations Bad Management Frame Handling The management block of the device can recognize management frames without preambles (preamble suppression). However receives a bad manage- ment frame, it will go into a Bad Management Frame state ...

Page 25

... The Physical Address of the PHY is set using the pins defined as PHYAD[4:2]. These input signals are strapped externally and sampled as reset is negated. The PHYAD[1:0] will be decoded by the NetPHY™ 4LP device to address its internal four PHY channels. All registers are available on a per port basis. ...

Page 26

... Disable Auto-Negotiation process Power down. The NetPHY™ 4LP device will shut off all blocks except for MDIO/MDC interface Power Down 0 = Normal operation Electrically isolate the PHY from MII. However, PHY is still able to respond to MDC/MDIO Isolate 0 = Normal operation Restart Auto-Negotiation process. ...

Page 27

... Able to perform Auto-Negotiation function, its value is determined by ANEGA pin Unable to perform Auto-Negotiation function Link is established, however, if the NetPHY™ 4LP device link fails, this bit will be cleared and remain cleared until register is read via management interface Link is down. ...

Page 28

... MAC control sublayer and the pause function as specified in clause 31 and annex 802.3u MAC-based full duplex flow control. The NetPHY™ 4LP device does not support 100BASE-T4 function, i.e., this bit ties to zero 100BASE-TX with full duplex 100BASE-TX full duplex ability. ...

Page 29

Auto-Negotiation Link Partner Ability Register in Base Page Format (Register 5) Table 12. Auto-Negotiation Link Partner Ability Register in Base Page Format (Register 5) Reg Bit Name 5 15 Next Page 5 14 Acknowledge 5 13 Remote Fault 5 12:11 ...

Page 30

... TOG_TX 7 10:0 CODE Reserved Registers (Registers 8-15, 22-23, 25-31) The NetPHY™ 4LP device contains reserved registers at addresses 8-15, 22-23, 25-31. These registers should be ignored when read and should not be written at any time. 30 Description Ignore when read Fault detected by parallel detection logic, this fault is due to more than one technology detecting concurrent link up condition ...

Page 31

Miscellaneous Features Register (Register 16) Table 16. Miscellaneous Features Register (Register 16) Reg Bit Name Description 16 15 Reserved Write factory use only INT is forced signal an interrupt ...

Page 32

Diagnostic Register (Register 18) Table 18. Diagnostic Register (Register 18) Reg Bit Name Description 18 15:12 Reserved Ignore when read. This bit indicates the result of the Auto-Negotiation for duplex arbitration DPLX 1 = Full Duplex ...

Page 33

... Force and the data rate must be 100 Mbps 100BASE-TX Link Normal Operation Disable Jabber function in PHY Jabber Disable 0 = Enable Jabber function in PHY Reserved Write as 0, ignore when read Activity only responds to receive operation. Activity LED Activity responds to Receive and transmit. Configuration In repeater mode, this bit will be ignored ...

Page 34

A BSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . .-55°C to +150°C Ambient Temperature Under Bias . . . -55°C to +150°C Supply Voltage ( ...

Page 35

Symbol Parameter Description RX± 10BASE-T Squelch Threshold V TSQ RX± Post-Squelch Differential V THS Threshold 10BASE-T (Note 8) 10BASE-T RX± Differential V RXDTH Switching Threshold (Note 8) 10BASE-T Near-End Peak V TX10NE Differential Voltage (Note 9) Output Leakage Current I ...

Page 36

SWITCHING WAVEFORMS Key to Switching Waveforms SWITCHING WAVEFORMS RX± 36 WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from May Will be Change Changing from L to ...

Page 37

V DD Ω 49.9 Ω 49.9 TX+ TX- 0.01 µF Figure 11. MLT-3 and 10BASE-T Test Load with 1:1 Transformer Ratio V DD Ω 78.1 Ω 78.1 TX+ TX- 0.01 µF Figure 12. MLT-3 and 10BASE-T Test Load with 1.25:1 ...

Page 38

V TX10NE TX± 10BASE-T 0 Figure 14. Near-End 10BASE-T Waveform Pin 5 V Test Load Figure 15. Recommended PECL Test Loads 82.5 Ω Pin 130 Ω 3.3 V Test Load Am79C875 22236G-16 DD ...

Page 39

SWITCHING CHARACTERISTICS System Clock Signal Symbol Parameter Description t REFCLK Period CLK t REFCLK Width HIGH CLKH t REFCLK Width LOW CLKL t REFCLK Rise Time CLR t REFCLK Fall Time CLF Notes: 1. Parametric values are the same for ...

Page 40

MII Management Signals Symbol Parameter Description t MDC Period MDPER t MDC Pulse Width HIGH MDWH t MDC Pulse Width LOW MDWL t MDIO Delay From Rising Edge of MDC MDPD t MDIO Setup Time to Rising Edge of MDC ...

Page 41

Independent RMII Mode Signals 100 Mbps RMII Transmit Symbol Parameter Description t TX_EN[X], TXD[X]_[1:0] Setup Time to REFCLK Rising Edge RS100 t TX_EN[X], TXD[X]_[1:0] Hold time From REFCLK Rising Edge RH100 t Transmit Latency TX_EN[X] Sampled by REFCLK to First ...

Page 42

Mbps RMII Receive Symbol Parameter Description t CRS_DV[X] HIGH After First Bit of /J/ RJC100 RXD[X]_[1:0], CRS_DV[X] Delay After the Rising Edge of t RCR100 REFCLK t First Bit of /T/ to CRS_DV[X] LOW RTC100 Note: CRS_DV[X] is asynchronous ...

Page 43

Mbps RMII Transmit Symbol Parameter Description t TX_EN[X], TXD[X]_[1:0] Setup Time to REFCLK Rising Edge RS10 t TX_EN[X], TXD[X]_[1:0] Hold time From REFCLK Rising Edge RH10 Transmit Latency TX_EN[X] Sampled by REFCLK to Start of t RTP10 Packet t ...

Page 44

Mbps RMII Receive Symbol Parameter Description t CRS_DV[X] HIGH After Start of Packet RSPC10 RXD[X]_[1:0], CRS_DV[x] Delay After the Rising Edge of t RCR10 REFCLK t End of Packet to CRS_DV[X] LOW REPC10 RX± CRS_DV[X] REFCLK RXD[X]_[1:0] Figure 26. ...

Page 45

... PHYSICAL DIMENSIONS* PQR100 (measured in millimeters) *For reference only. BSC is an ANSI standard for Basic Space Centering. Am79C875 45 ...

Page 46

... Revision B.4 Errata Summary The NetPHY™ 4LP device has a total of 5 errata, all of which are minor and should not cause concern. All informa- tion below should be used in conjunction with the NetPHY™ 4LP Final Datasheet PID 22236, available on the AMD web site (www.amd.com). Errata for NetPHY™ ...

Page 47

B4.5) Full Duplex operation with Auto-Negotiation Disabled SYMPTOM: If Auto-Negotiation is disabled, the device cannot be pin-strapped to full-duplex. LEDDPX[2]/ DPLX (Pin 41) should set the duplex at reset if LEDACT_LINK/ANEGA (Pin 39) is LOW at re- set. Instead, all ...

Page 48

... MII Management signals: MDIO delay changed to 20ns (max), MDIO setup time changed to 4ns (min), MDIO hold time changed to 3ns (max) Revision Specified using resistors in the range of 1 KΩ to 4.7 KΩ for setting the PHYAD pins. Figure 8 reflects the correct resistors. 2. Added bit 10, Flow Control Support, to Register 5. ...

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