NLXT901PC.E2 S E001 Intel, NLXT901PC.E2 S E001 Datasheet - Page 39
NLXT901PC.E2 S E001
Manufacturer Part Number
NLXT901PC.E2 S E001
Description
Manufacturer
Intel
Datasheet
1.NLXT901PC.E2_S_E001.pdf
(46 pages)
Specifications of NLXT901PC.E2 S E001
Lead Free Status / RoHS Status
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4.3
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
TPIP/TPIN
or DIP/DIN
NOTE:
Figure 29. Mode 3 RCLK/Start-of-Frame Timing (LXT901 only)
Figure 30. Mode 3 RCLK/End-of-Frame Timing (LXT901 only)
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
RCLK
or DIP/DIN
TPIP/TPIN
RXD
CD
RCLK
RXD
CD
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Figures 29 - 36
1
1
t
CD
0
0
1
1
t
RD
1
0
0
t
DATA
0
1
1
1
0
0
0
1
1
Universal 10BASE-T and AUI Transceivers — LXT901/907
0
1
0
1
0
0
t
1
1
RDS
1
t
CDOFF
1
0
0
0
1
0
1
0
t
RDH
0
1
0
0
27 bits
0
1
1
0
0
1
1
1
1
0
1
39
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