CY7B923-JI Cypress Semiconductor Corp, CY7B923-JI Datasheet

CY7B923-JI

Manufacturer Part Number
CY7B923-JI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7B923-JI

Lead Free Status / RoHS Status
Not Compliant

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Cypress Semiconductor Corporation
Document #: 38-02017 Rev. *E
Features
• Fibre-Channel-compliant
• IBM ESCON
• DVB-ASI-compliant
• ATM-compliant
• 8B/10B-coded or 10-bit unencoded
• Standard HOTLink
• High-speed HOTLink: 160–400 Mbps for high-speed
• Low-speed HOTLink: 150–160 Mbps for low-cost fiber
• TTL synchronous I/O
• No external phase locked-loop (PLL) components
• Triple PECL 100K serial outputs
• Dual PECL 100K serial inputs
• Low power: 350 mW (Tx), 650 mW (Rx)
• Compatible with fiber-optic modules, coaxial cable, and
• Built-in Self-Test (BIST)
• Single +5V supply
• 28-pin SOIC/PLCC/LCC
• Pb-Free Packages Available
• 0.8µ BiCMOS
applications
applications
twisted pair media
CY7B923 Transmitter Logic Block Diagram
BISTEN
MODE
CKW
RP
-compliant
GENERATOR
CLOCK
LOGIC
ENN
TEST
: 160–330 Mbps
ENA
(D
D
INPUT REGISTER
b–h
0–7
)
ENCODER
ENABLE
SHIFTER
SC/D (D a )
SVS(D j )
FOTO
198 Champion Court
OUTA
OUTB
OUTC
INB (INB+)
CY7B933 Receiver Logic Block Diagram
HOTLink
SI(INB− )
REFCLK
Functional Description
The CY7B923 HOTLink
Receiver are point-to-point communications building blocks
that transfer data over high-speed serial links (fiber, coax, and
twisted pair). Standard HOTLink data rates range from 160 to
330 Mbits/second. Higher speed HOTLink is also available for
high-speed applications (160–400 Mbits/second), as well as,
for
Mbits/second operations). Figure 1 illustrates typical connec-
tions to host systems or controllers.
Eight bits of user data or protocol information are loaded into
the HOTLink transmitter and are encoded. Serial data is
shifted out of the three differential positive ECL (PECL) serial
ports at the bit rate (which is ten times the byte rate).
The HOTLink receiver accepts the serial bit stream at its differ-
ential line receiver inputs and, using a completely integrated
PLL Clock Synchronizer, recovers the timing information
necessary for data reconstruction. The bit stream is deseri-
alized, decoded, and checked for transmission errors.
Recovered bytes are presented in parallel to the receiving host
along with a byte-rate clock.
The 8B/10B encoder/decoder can be disabled in systems that
already encode or scramble the transmitted data. I/O signals
are available to create a seamless interface with both
asynchronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A BIST pattern generator and checker allows
testing of the transmitter, receiver, and the connecting link as
a part of a system diagnostic check.
HOTLink devices are ideal for a variety of applications where
a parallel interface can be replaced with a high-speed
point-to-point serial link. Applications include interconnecting
workstations, servers, mass storage, and video transmission
equipment.
BISTEN
MODE
INA+
INA−
A/B
SO
RF
low-cost
LOGIC
San Jose
TEST
PECL
TTL
applications,
CLOCK
SYNC
Transmitter/Receiver
,
CKR
CA 95134-1709
Transmitter and CY7B933 HOTLink
DATA
RDY
Revised August 29, 2005
HOTLink-155
(Q
DECODER
REGISTER
DECODER
REGISTER
FRAMER
SHIFTER
OUTPUT
Q
b–h
0–7
)
SC/D (Q a )
CY7B923
CY7B933
408-943-2600
RVS(Q j )
(150–160

Related parts for CY7B923-JI

CY7B923-JI Summary of contents

Page 1

... Low power: 350 mW (Tx), 650 mW (Rx) • Compatible with fiber-optic modules, coaxial cable, and twisted pair media • Built-in Self-Test (BIST) • Single +5V supply • 28-pin SOIC/PLCC/LCC • Pb-Free Packages Available • 0.8µ BiCMOS CY7B923 Transmitter Logic Block Diagram SC 0– b–h SVS ...

Page 2

... HOST CY7B923 Transmitter Pin Configurations SOIC Top View OUTB− OUTC− OUTC CCN BISTEN 5 24 GND 6 23 MODE 7 22 7B923 CCQ 9 20 SVS PLCC/LCC Top View 2726 28 BISTEN 5 GND 6 MODE 7 7B923 CCQ SVS 1213 14 15 1718 Document #: 38-02017 Rev. *E SERIAL LINK Figure 1 ...

Page 3

... Pin Descriptions CY7B923 HOTLink Transmitter Name I/O Description D TTL In Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW (or 0− the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (K28.5) is sent. ...

Page 4

... CY7B923 HOTLink Transmitter (continued) Name I/O Description V Power for output drivers. CCN V Power for internal circuitry. CCQ GND Ground. CY7B933 HOTLink Receiver Name I/O Description Q TTL Out Q Parallel Data Output. Q 0−7 0– synchronously with CKR. When MODE is HIGH − h SC/D (Q ...

Page 5

... V Power for internal circuitry. CCQ GND Ground. CY7B923 HOTLink Transmitter Block Diagram Description Input Register The Input register holds the data to be processed by the HOTLink transmitter and allows the input timing to be made consistent with standard FIFOs. The Input register is clocked by CKW and loaded with information on the D SVS pins ...

Page 6

... Test logic includes the initialization and control for the Built-In Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic to properly select the data encoding. Test logic is discussed in more detail in the CY7B923 HOTLink Transmitter Operating Mode Description. CY7B933 HOTLink Receiver Block Diagram Description Serial Data Inputs Two pairs of differential line receivers are the inputs for the serial data stream. INA± ...

Page 7

... Mbytes per second (40 Mbytes per second for –400 devices) over several types of serial interface media. Figure 7 illus- trates the flow of data through the HOTLink CY7B923 trans- mitter pipeline. Data is latched into the transmitter on the rising edge of CKW when enabled by ENA or ENN asserted LOW with a 60% LOW/40% HIGH duty cycle when ENA is LOW ...

Page 8

... More information on interfacing HOTLink to various media can be found in the HOTLink Design Considerations application note. CY7B923 HOTLink Transmitter Operating Mode Description In normal operation, the Transmitter can operate in either of two modes. The Encoded mode allows a user to send and receive eight-bit data and control information without first converting it to transmission characters ...

Page 9

... CC This results in a power savings of around 5 mA for each unused pair. In systems that require the outputs to be shut off during some periods when link transmission is prohibited (e.g., for laser CY7B923 CY7B933 CLOCKED FIFO 7C44X/5X Q ENR CKR 0– ...

Page 10

... Random Jitter (R measured while sending a continuous K28.7 (C7.0). Transmitter Test Mode Description The CY7B923 Transmitter offers two types of test mode operation, BIST mode and Test mode normal system application, the Built-In Self-Test (BIST) mode can be used to check the functionality of the Transmitter, the Receiver, and the link connecting them ...

Page 11

... SVS input, or allowing the trans- mitter BIST loop to run while the Receiver runs in normal mode. The BIST loop includes deliberate violation symbols and will adequately test the RVS function. CY7B923 CY7B933 CY7B923 OUTA OUTB OUTC CY7B933 SO DON'T CARE ...

Page 12

... The only restrictions upon the data encoding method is that it contain suitable transition density for the Receiver PLL data synchronizer (one per 10-bit byte) and that it be compatible with the transmission media. CY7B923 CY7B933 – context control bit (SC/D), and a system ...

Page 13

... Note: Acquisition time is measured from worst-case phase or frequency change to zero phase and frequency error result of the receiver’s wide jitter tolerance, valid data will appear at the receiver’s outputs a few byte times after a worst-case phase change. CY7B923 CY7B933 RVS SC/D Qouts Name 0 00-FFD0.0-31.7 ...

Page 14

... CC The bit labeled A in the description of the 8B/10B Transmission Code corresponds to bit 0 in the numbering scheme of the FC-2 specification, B corresponds to bit 1, as shown below. FC-2 bit designation— HOTLink D/Q designation— 7 8B/10B bit designation— H CY7B923 CY7B933 ...

Page 15

... It is also pos- itive at the end of the 6-bit sub-block if the 6-bit sub-block is 000111, and it is positive at the end of the 4-bit sub-block if the 4-bit sub-block is 0011. 2. Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones also CY7B923 CY7B933 Page ...

Page 16

... Transmission Character in which the error occurred. Table 2 shows an example of this behavior. Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CY7B923 CY7B933 Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 00010 02 ...

Page 17

... CY7B923 CY7B933 Page ...

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... CY7B923 CY7B933 Page ...

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Page 25

... Code Rule Violation and SVS Tx Pattern 111 00000 100111 111 00001 001111 111 00010 110000 Running Disparity Violation Pattern 111 00100 110111 CY7B923 CY7B933 Current RD+ fghj abcdei fghj 0100 110000 1011 1001 110000 0110 0101 110000 1010 0011 110000 ...

Page 26

... Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Output Current into TTL Outputs (LOW) ......................30 mA Output Current into PECL Outputs (HIGH) ................–50 mA CY7B923/CY7B933 Electrical Characteristics Parameter Description TTL OUTs, CY7B923: RP; CY7B933 Output HIGH Voltage OHT V Output LOW Voltage OLT ...

Page 27

... CY7B923/CY7B933 Electrical Characteristics Parameter Description Miscellaneous [11] I Transmitter Power Supply CCT Current [12] I Receiver Power Supply CCR Current [13] Capacitance Parameter Description C Input Capacitance IN AC Test Loads and Waveforms OUTPUT R1 = 910Ω 510Ω < (Includes fixture and probe capacitance) (a) TTL AC Test Load 3 ...

Page 28

... CKW, but not RP function or timing −2.0V, over the operating range. CC /10 if data is being received. See note. CKW , SC/D, and RVS) are loaded with similar DC and AC loads. 0−7 CY7B923 CY7B933 [7] 7B923 7B923-400 Max Min. Max Min. ...

Page 29

... REFCLK Clock Pulse HIGH CPXH t REFCLK Clock Pulse LOW CPXL t Propagation Delay (note PECL and TTL DS [26] thresholds) [13, 27] t Static Alignment SA [13, 28] t Error Free Window EFW Switching Waveforms for the CY7B923 HOTLink Transmitter CKW ENA D – SC/D, SVS, BISTEN RP CKW ENN D – ...

Page 30

... BB 26 NOTE SO Static Alignment /2 − ± INA , ± INB SAMPLE WINDOW Document #: 38-02017 Rev CPRH t CPRL t PRH t PRF CPXL t CPXH t DS 1.5V Error-free Window /2 − CY7B923 CY7B933 t CKR ROH t CKX t EFW ± INA ± INB t B BIT CENTER BIT CENTER Page ...

Page 31

... DATA LATCHED IN CKW ENA D , 0−7 SC/D, DATA SVS RP ± OUTX Ordering Information Speed Ordering Code Standard CY7B923-JC CY7B923-JXC CY7B923-JI CY7B923-JXI CY7B923-SC CY7B923-SXC 400 CY7B923-400JC CY7B923-400JXC CY7B923-400JI 155 CY7B923-155JC CY7B923-155JI Standard CY7B933-JC CY7B933-JXC CY7B933-JI CY7B933-JXI CY7B933-SC CY7B933-SXC CY7B933-SXI 400 CY7B933-400JC CY7B933-400JXC ...

Page 32

... REFERENCE JEDEC MO-119 0.419[10.64] 0.291[7.39] PACKAGE WEIGHT 0.85gms 0.300[7.62] 28 0.026[0.66] 0.032[0.81] SEATING PLANE 0.092[2.33] 0.105[2.67] 0.004[0.10] * 0.004[0.10] 0.0118[0.30] CY7B923 CY7B933 DIMENSIONS IN INCHES MIN. MAX. 0.013 0.021 0.390 0.430 0.020 MIN. 0.090 0.120 0.165 51-85001-*A 0.180 MIN. MAX. PART # S28.3 STANDARD PKG. ...

Page 33

... Changed INA± pin description to include what to do with unused pairs of inputs. Changed Equation in note 6–old one made no sense. BSS Changed Hotlink Transmitter/Receiver to Hotlink OOR Removed all references to Military parts (Obsolete): CY7B923-LMB, CY7B933-LMB KKV Minor change: reset Valid Data Characters (SC/D = LOW) table format to single-column pages ...

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