SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 19

• Manufacturer Part Number: SLXT973QC.A2
• Manufacturer: Intel

Specifications of SLXT973QC.A2

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Table 4. LXT973 Network Interface Signal Descriptions (Continued)
Table 5. LXT973 Global Control & Configuration Signal Descriptions
Pin #
Pin #
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
78
79
13
52
53
54
55
56
57
15
11
12
67
68
71
72
75
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
TxSLEW0
TxSLEW1
RESET
ADDR4
ADDR3
ADDR2
ADDR1
TEST_0
TEST_1
REFCLK
LED_CFG0
LED_CFG1
DPBP_1
DPBN_1
DPAN_1
DPAP_1
Names
Names
Signal
Signal
SD1
RX+
TX+
TX-
RX-
Type
Op
TP
-
I
I
I
I
I
I
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
1
Fiber
RX+
TX+
RX-
Tx Output Slew Controls 0 & 1. These pins select the TX output slew rate
(rise and fall time) for both cores in the LXT973 device.
The various options are defined in Register bits 27.11:10. The TxSLEW pins set
the power-on value of these register bits.
Reset. This active Low input is OR’d with Control Register bit 0.15.
Address <4:1>. Sets device Port 0 PHY address. Note that ADDR0 is set
internally so that Port 1 is always “1” address higher than Port 0.
Test Pins. Tie Low for normal operation.
Master Clock Input. A 25 MHz, 50 ppm clock is input here to act as the master
clock. Full clock requirements are detailed in the Clock Requirements section of
the Functional Description. See
page
LED Configuration 0 & 1. These pins are used to select one of four LED
modes. The decode or each mode is shown below:
TX-
Op
LED_CFG0
-
0
1
0
1
28.
Port
1
1
1
1
-
LED_CFG1
Type
Pair
B
B
A
A
-
0
0
1
1
AI/AO,
AI/AO,
Type
SL
SL
I
1
Signal Description
LEDn_1
Speed
Speed
Speed
Section 3.4.2, “Clock Requirements” on
Link
Twisted-Pair/Fiber Pair B, Positive &
Negative - Port 1. Differential pair produces
or receives IEEE 802.3-compliant pulses for
either 100BASE-TX or 10BASE-T.
Also acts as transmitter in Fiber mode.
Twisted-Pair/Fiber Pair A, Positive &
Negative - Port 1. Differential pair produces
or receives IEEE 802.3-compliant pulses for
either 100BASE-TX or 10BASE-T.
Also acts as receiver in Fiber mode.
Signal Detect. This signal is used for signal
quality indication in Fiber mode. In twisted-
pair mode, this pin should be tied Low.
Link/MII Isolate
Link/Activity
Signal Description
LEDn_2
Receive
Link
Duplex/Collision
Duplex/Collision
LEDn_3
Transmit
Duplex
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