SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 24

• Manufacturer Part Number: SLXT973QC.A2
• Manufacturer: Intel

Specifications of SLXT973QC.A2

• Lead Free Status / RoHS Status: Not Compliant

LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
3.2.1.3
3.3
3.3.1
3.3.2
3.3.3
24
Fiber Interface
The LXT973 provides a PECL interface that complies with the ANSI X3.166 specification. This
interface is suitable for driving a fiber-optic coupler (see
Fiber ports cannot be enabled via auto-negotiation and must be enabled via the Global Hardware
Control Interface pins or MDIO registers. Using external circuitry, the LXT973 can interface the
fiber transceiver with 2.5V or 3.3V supply voltages. Fiber mode per port may be selected using
Register bit 16.0. Please refer to
MII Operation
The LXT973 device implements the Media Independent Interface (MII) as defined in the IEEE
802.3 standard. Separate channels are provided for transmitting data from the MAC to the LXT973
(TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own
clock, data bus, and control signals. Nine signals are used to pass received data to the MAC:
RXD<3:0>, RXCLK, RXDV, RXER, COL and CRS. Seven signals are used to transmit data from
the MAC: TXD<3:0>, TXCLK, TXEN, and TXER.
The LXT973 supplies both clock signals as well as separate outputs for carrier sense and collision.
Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
MII Clocks
The LXT973 is the master clock source for data transmission and supplies both MII clocks
(RXCLK and TXCLK). It automatically sets the clock speeds to match link conditions. When the
link is operating at 100 Mbps, the clocks are set to 25 MHz. When the link is operating at 10 Mbps,
the clocks are set to 2.5 MHz. The transmit data and control signals must always be synchronized
to TXCLK by the MAC. The LXT973 samples these signals on the rising edge of TXCLK.
Transmit Enable
The MAC must assert TXEN at the same time as the first nibble of preamble, and de-assert TXEN
after the last bit of the packet.
Receive Data Valid
The LXT973 asserts RXDV when it receives a valid packet. Timing changes depend on line
operating speed:
•
•
For 100BASE-TX links, RXDV is asserted from the first nibble of preamble to the last nibble
of the data packet.
For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble
of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
Table 4 on page 18
for correct pin assignments.
Figure 14 on page
46).
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002
Datasheet