SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 36
Manufacturer Part Number
Specifications of SLXT973QC.A2
Lead Free Status / RoHS Status
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Figure 10. Protocol Sublayers
100BASE-X Protocol Sublayer Operations
In the 7-layer OSI communications model, the LXT973 is a Physical Layer 1 (PHY) device. The
LXT973 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA),
and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE
802.3u specification. The following paragraphs discuss the LXT973 operation from the reference
model point of view.
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE
symbols to the PMD-layer line driver as long as TXEN is de-asserted. For 10BASE-T operation,
the PCS layer merely provides a bus interface and serialization/de-serialization function.
10BASE-T operation does not use the 4B/5B encoder.
When the MAC asserts TXEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-of-
Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues
to encode the remaining MII data until TXEN is de-asserted. It then returns to supplying IDLE
symbols to the line driver.
The PCS layer performs the opposite function in the receive direction by substituting two preamble
nibbles for the SSD.
The LXT973 handles dribble bits in all modes. If one through four dribble bits are received, the
nibble is passed across the MII, and padded with ones if necessary. If five through seven dribble
bits are received, the second nibble is not sent to the MII bus.
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002