SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 38
Manufacturer Part Number
Specifications of SLXT973QC.A2
Lead Free Status / RoHS Status
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Fiber PMD Sublayer
The LXT973 provides a PECL interface for connection to an external fiber-optic transceiver. (The
external transceiver provides the PMD function for fiber media.) The device uses an NRZI format
for the fiber interface. The fiber interface operates at 100 Mbps only and does not support 10 Mbps
Far End Fault Indications
The LXT973 Signal Detect pins independently detect signal faults from the local fiber transceivers
via the SD pins. The device also uses Register bit 1.4 to report Remote Fault indications received
from its link partner. The device ORs both fault conditions to set Register bit 1.4. This bit is set
once and cleared when read.
Either fault condition causes the LXT973 to drop the link unless Forced Link Pass is selected
(Register bit 16.14 = 1). A link-down condition is then reported via status bits.
In response to locally detected signal faults (SD activated by the local fiber transceiver), the
affected port can transmit the Far End Fault code if a fault code transmission is enabled by Register
The occurrence of a Far End Fault causes all transmission of data from the Reconciliation Sublayer
to stop and the Far End fault code to begin. The Far End Fault code consists of 84 “1s” followed by
a single “0”, and is repeated until the Far End Fault condition is removed.
10 Mbps Operation
The LXT973 operates as a standard 10BASE-T transceiver and supports all the standard 10 Mbps
functions. During 10BASE-T operation, the LXT973 transmits and receives Manchester-encoded
data across the network link. When the MAC is not actively transmitting data, the device sends out
link pulses on the line.
In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded
signals received from the network are decoded by the LXT973 and sent across the MII to the MAC.
The LXT973 automatically detects and corrects for an inverted receive signal. Reversed polarity is
detected if eight inverted link pulses or four inverted End-of-Frame (EOF) markers are received
consecutively. If link pulses or data are not received by the maximum receive time-out period, the
polarity state is reset to a non-inverted state.
When Register bit 16.2 = 1, transmission of the Far End Fault code is enabled. The LXT973
transmits Far End Fault code if fault conditions are detected by the Signal Detect pins.
When Register bit 16.2 = 0, the LXT973 does not transmit Far End Fault code. It continues to
transmit IDLE code and may or may not drop link, depending on the setting for Register bit
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002