SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 41



Manufacturer Part Number

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Application Information
Design Recommendations
The LXT973 is designed to comply with IEEE 802.3 requirements to provide outstanding receive
Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance from
the LXT973, attention to detail and good design practices are required. Refer to the LXT973 Design
and Layout Guide for detailed design and layout information.
General Design Guidelines
Adherence to generally accepted design practices is essential to minimize noise levels on power
and ground planes. Up to a maximum noise level of 50 mV is considered acceptable. High-
frequency switching noise can be reduced, and its effects eliminated, by following these simple
guidelines throughout the design:
Power Supply Filtering
Power supply ripple and digital switching noise on the VCC plane may cause EMI problems and
degrade line performance. To minimize ground noise as much as possible, use good general
techniques and filter the VCC plane. It is difficult to predict in advance the performance of any
design, although certain factors greatly increase the risk of having problems:
Intel recommends filtering the power supply to the analog VCC pins of the LXT973. This has two
benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT973,
helping with line performance. Second, if the VCC planes are laid out correctly, digital switching
noise is kept away from external connectors, reducing EMI problems.
Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC
or ground plane that is not located adjacent to the signal layer.
Use ample bulk and de-coupling capacitors throughout the design (a value of 0.01 F is
recommended for de-coupling caps).
Provide ample power and ground planes.
Provide termination on all high-speed switching signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Route high-speed signals next to a continuous, unbroken ground plane.
Filter and shield DC-to-DC converters, oscillators, etc.
Do not route any digital signals between the LXT973 and the RJ-45 connectors at the edge of
the board.
Do not extend any circuit power and ground planes past the center of the magnetics or to the
edge of the board. Use this area for chassis ground, or leave it void.
Poorly-regulated or over-burdened power supplies.
Wide data busses (32-bits+) running at a high clock rate.
DC-to-DC converters.
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

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