SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 42



Manufacturer Part Number

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
The recommended implementation is to break the VCC plane into two sections. The digital section
supplies power to the VCCD and VCCIO pins of the LXT973. The analog section supplies power
to the VCCR, VCCT, VCCPECL pins. The break between the two planes should run underneath
the device. In designs with more than one LXT973 device, a single continuous analog VCC plane
can be used to supply them all.
The digital and analog VCC planes should be joined at one or more points by ferrite beads. The
beads should produce at least a 100 impedance at 100 MHz. Beads should be placed so that
current flow is evenly distributed. The maximum current rating of the beads should be at least
150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10 F) should
be placed on each side of each bead. In addition, a high-frequency bypass cap (0.01 F) should be
placed near each analog VCC pin.
Power and Ground Plane Layout Considerations
Great care needs to be taken when laying out the power and ground planes.
Chassis Ground
For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the
board and is isolated via moats and keep-out areas from all circuit-ground planes and active
signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used
to terminate unused signal pairs (Bob Smith termination). In single-point grounding applications,
provide a single connection between chassis and circuit grounds with a 2 kV isolation capacitor. In
multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide
2 kV isolation to the Bob Smith termination.
MII Terminations
Series termination resistors are required on all the output signals driven by the LXT973. Keep all
traces orthogonal and as short as possible. Whenever possible, route the clock traces evenly
between the longest and shortest data routes. This minimizes round-trip, clock-to-data delays and
allows a larger margin to the setup and hold requirements. Please refer to the LXT973 Design and
Layout Guide for series resistor values.
The Fiber Interface
The fiber interface consists of a PECL transmit and receive pair to an external fiber-optic
transceiver. The transmit and receive pair should be DC-coupled to the transceiver, and biased
appropriately. Refer to the fiber transceiver manufacturer’s recommendations for termination
Follow the guidelines in the LXT973 Design and Layout Guide for locating the split between
the digital and analog VCC planes.
Keep the digital VCC plane away from the DPAP/N_n and DPBP/N_n signals, the magnetics,
and the RJ-45 connectors.
Place the layers so that the DPAP/N_n and DPBP/N_n signals can be routed near or next to the
ground plane.
Figure 14 on page 46
shows a typical example.
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002

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