DP83848CVVX National Semiconductor, DP83848CVVX Datasheet
DP83848CVVX
Specifications of DP83848CVVX
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DP83848CVVX Summary of contents
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... Industrial Controls and Factory Automation • General Embedded Applications System Diagram MPU/CPU MII/RMII/SNI ® PHYTER is a registered trademark of National Semiconductor. © 2008 National Semiconductor Corporation ® - Commercial Temperature Features • Low-power 3.3V, 0.18 m CMOS technology • Low power consumption < 270mW Typical • ...
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TX_DATA TX_CLK 10BASE-T & 100BASE-TX Transmit Block DAC Auto-MDIX www.national.com MII/RMII/SNI SERIAL MANAGEMENT MII/RMII/SNI INTERFACES MII Registers Auto-Negotiation State Machine Clock Generation TD± RD± REFERENCE CLOCK Figure 1. DP83848C Functional Block Diagram 2 RX_CLK RX_DATA 10BASE-T & 100BASE-TX Receive Block ...
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... Auto-Negotiation Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.5 Enabling Auto-Negotiation via Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.3 PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.3.1 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.4.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.2 LED Direct Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2 ...
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... Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 7.1.1 Basic Mode Control Register (BMCR 7.1.2 Basic Mode Status Register (BMSR 7.1.3 PHY Identifier Register #1 (PHYIDR1 7.1.4 PHY Identifier Register #2 (PHYIDR2 7.1.5 Auto-Negotiation Advertisement Register (ANAR 7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page ...
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... Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.2.23 100BASE-TX Signal Detect Timing 8.2.24 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.2.25 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.2.26 RMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.2.27 RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.2.28 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.2.29 25 MHz_OUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.2.30 100 Mb TX_CLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . www.national.com ...
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... Figure 1. DP83848C Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 6. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . . 28 Figure 9 ...
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... Table 11. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 12. Basic Mode Control Register (BMCR), address 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Table 13. Basic Mode Status Register (BMSR), address 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 14. PHY Identifier Register #1 (PHYIDR1), address 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 15. PHY Identifier Register #2 (PHYIDR2), address 0x03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 16. Negotiation Advertisement Register (ANAR), address 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 17. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 . . . . . . . .46 Table 18 ...
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... Pin Layout PFBIN2 RX_CLK RX_DV/MII_MODE CRS/CRS_DV/LED_CFG RX_ER/MDIX_EN COL/PHYAD0 RXD_0/PHYAD1 RXD_1/PHYAD2 RXD_2/PHYAD3 RXD_3/PHYAD4 IOGND IOVDD33 www.national.com DP83848C Top View NS Package Number VBH48A 8 RBIAS 24 PFBOUT 23 AVDD33 22 RESERVED 21 RESERVED 20 AGND 19 PFBIN1 AGND ...
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... The maximum clock rate is 25 MHz with no minimum clock rate. 30 MANAGEMENT DATA I/O: Bi-directional management instruc- tion/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 k Pin # Description 1 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2 ...
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... RXDV is asserted in 100 Mb/s mode. This pin is not required to be used by a MAC, in either MII or RMII mode, since the Phy is required to corrupt data on a receive error. This pin is not used in SNI mode. 43 MII RECEIVE DATA: Nibble wide receive data signals driven syn- chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2 ...
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Clock Interface Signal Name Type 25MHz_OUT O 1.4 LED Interface See Table 3 for LED Mode Selection. Signal Name Type LED_LINK LED_SPEED LED_ACT/COL Pin # Description ...
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... MII Isolate Mode. The MII isolate mode must be se- 46 lected by strapping Phy Address 0; changing to Address 0 by reg- ister write will not put the Phy in the MII isolate mode. Please refer to section 2.3 for additional information. PHYAD0 pin has weak internal pull-up resistor. ...
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Signal Name Type AN_EN (LED_ACT/COL AN_1 (LED_SPEED) AN_0 (LED_LINK) MII_MODE (RX_DV SNI_MODE (TXD_3) LED_CFG (CRS MDIX_EN (RX_ER Pin # Description 26 Auto-Negotiation Enable: When high, this enables Auto-Negoti- ...
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Mb/s and 100 Mb/s PMD Interface Signal Name Type TD-, TD+ I/O RD-, RD+ I/O 1.8 Special Connections Signal Name Type RBIAS PFBOUT PFBIN1 PFBIN2 RESERVED I/O RESERVED I/O 1.9 Power Supply Pins Signal Name IOVDD33 IOGND DGND ...
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... PWR_DOWN/INT 8 RESERVED 9 RESERVED 10 RESERVED 11 RESERVED 12 RESERVED AGND PFBIN1 19 AGND 20 RESERVED 21 RESERVED 22 AVDD33 23 PFBOUT 24 RBIAS 25 25MHz_OUT 26 LED_ACT/COL/AN_EN 27 LED_SPEED/AN1 28 LED_LINK/AN0 29 RESET_N 30 MDIO 31 MDC 32 IOVDD33 IOGND 36 DGND 37 PFBIN2 38 RX_CLK 39 RX_DV/MII_MODE 40 CRS/CRS_DV/LED_CFG VBH48A Pin # Pin Name 41 RX_ER/MDIX_EN 42 COL/PHYAD0 43 RXD_0/PHYAD1 44 RXD_1/PHYAD2 45 RXD_2/PHYAD3 46 RXD_3/PHYAD4 47 IOGND 48 IOVDD33 15 www.national.com ...
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... The Speed Selection and Duplex Mode bits have no effect on the mode of oper- ation when the Auto-Negotiation Enable bit is set. The Link Speed can be examined through the PHY Status Register (PHYSTS) at address 10h after a Link is achieved. The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, Auto-Negotiation ability, and Extended Register Capability ...
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... This implementation complies with the corresponding IEEE 802.3 Auto-Negotiation and Crossover Specifications. Auto-MDIX is enabled by default and can be configured via strap or via PHYCR (0x19h) register, bits [15:14]. Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs. Forced crossover can be achieved through the FORCE_MDIX bit, bit 14 of PHYCR (0x19h) register ...
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... Since the PHYAD[0] pin has weak internal pull-up resistor and PHYAD[4:1] pins have weak internal pull-down resis- tors, the default setting for the PHY address is 00001 (01h). Refer to Figure 2 for an example of a PHYAD connection to external components. In this example, the PHYAD strap- ping results in address 00011 (03h). RXD Function ...
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... LED output pins, the external components required for strapping and LED usage must be considered in order to avoid contention. multiplexed among the LEDs. The PHY Control Register (PHYCR) for the LEDs can also be selected through address 19h, bits [6:5]. See Table 3 for LED Mode selection. Table 3. LED Mode Select ...
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... BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit defaults to 0 (BIST fail) and will transition on a successful comparison error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit ...
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... The DP83848C incorporates the Reduced Media Indepen- dent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits at a time using the 50 MHz RMII_REF clock for both transmit and receive ...
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... Mb only devices. This is also referred 7-wire inter- face. While there is no defined standard for this interface based on early 10 Mb physical layer devices. Data is clocked serially at 10 MHz using separate transmit and receive paths. The following pins are used in SNI mode: — ...
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... Basic Mode Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management controller) deter- mines that all PHYs in the system support Preamble Sup- pression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction ...
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Architecture This section describes the operations within each trans- ceiver module, 100BASE-TX and 10BASE-T. Each opera- tion consists of several functional blocks and described in the following: — 100BASE-TX Transmitter — 100BASE-TX Receiver — 10BASE-T Transceiver Module 4.1 100BASE-TX ...
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Table 5. 4B5B Code-Group Encoding/Decoding DATA CODES IDLE AND CONTROL CODES INVALID CODES ...
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... NRZ data from the code-group encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83848C uses the PHY_ID (pins PHYAD [4:0]) to set a unique seed value. 4.1.3 NRZ to NRZI Encoder After the transmit data stream has been serialized and ...
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RX_DV/CRS RX_CLK RX_DATA VALID SSD DETECT Figure 7. 100BASE-TX Receive Block Diagram RXD[3:0] / RX_ER 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT DESCRAMBLER NRZI TO NRZ DECODER MLT-3 TO BINARY DECODER DIGITAL SIGNAL PROCESSOR ANALOG FRONT END RD 27 ...
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Digital Adaptive Equalization and Gain Control When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the fre- quency content of the transmitted signal can vary greatly ...
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Base Line Wander Compensation The DP83848C is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP- PMD defined “killer” pattern. BLW can generally be defined as the change ...
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Descrambler A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an identical data scrambling sequence (N) in order to recover the origi- nal unscrambled data (UD) from the scrambled data (SD) as ...
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... SQE is reported as a pulse on the COL signal of the MII. The SQE test is inhibited when the PHY is set in full duplex mode. SQE can also be inhibited by setting the HEARTBEAT_DIS bit in the 10BTSCR register. within 150 ns. Finally the signal must again exceed the original squelch level within a 150 ns to ensure that the input waveform will not be rejected ...
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Jabber Function The jabber function monitors the DP83848C's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmit- ter and disables the transmission if the transmitter ...
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Design Guidelines 5.1 TPI Network Circuit Figure 11 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. To the right is a partial list of recommended transformers important that the user realize that variations with ...
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... This limit is provided as a guideline for component selection and to guaranteed by production testing. Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance. www.national.com capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. ...
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... Stability Rise / Fall Time Jitter Jitter Symmetry 40% 1 This limit is provided as a guideline for component selection and to guaranteed by production testing. Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance. Parameter Min Frequency Frequency Tolerance Frequency Stability ...
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Interrupt Mechanisms The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting bit 1 (INTEN) of MICR (0x11h) will enable interrupts to be out- put, dependent on the interrupt mask set in the ...
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Reset Operation The DP83848C includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal opera- tion, the device can be reset by a hardware ...
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... Table 10. Register Map Tag BMCR Basic Mode Control Register BMSR Basic Mode Status Register PHYIDR1 PHY Identifier Register #1 PHYIDR2 PHY Identifier Register #2 ANAR Auto-Negotiation Advertisement Register ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page) ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page) ...
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Register Definition In the register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access SC — =Register sets on event occurrence and Self-Clears when event ends — RW/SC =Read Write access/Self Clearing bit — ...
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... Power Down Power down Normal operation. Setting this bit powers down the PHY. Only the register block is en- abled during a power down condition. This bit is OR’d with the input from the PWR_DOWN/INT pin. When the active low PWR_DOWN/INT pin is asserted, this bit will be set. ...
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Table 12. Basic Mode Control Register (BMCR), address 0x00 (Continued) Bit Bit Name Default 7 Collision Test 0, RW 6:0 RESERVED 0, RO Description Collision Test Collision test enabled Normal operation. When set, this bit will ...
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Basic Mode Status Register (BMSR) Table 13. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name 15 100BASE-T4 14 100BASE-TX Full Duplex 13 100BASE-TX Half Duplex 12 10BASE-T Full Duplex 11 10BASE-T Half Duplex 10:7 RESERVED 6 MF ...
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... The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848C. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num- ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National's IEEE assigned OUI is 080017h. ...
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... PAUSE functions as defined in Annex 31B. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolu- tion status is reported in PHYCR[13:12 Advertise that the DTE (MAC) has implemented both the op- tional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802 ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 17. Auto-Negotiation Link Partner Ability ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 18. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 Bit Bit Name ACK ACK2 11 Toggle 10:0 CODE <000 0000 0000>, 7.1.8 ...
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Table 19. Auto-Negotiate Expansion Register (ANER), address 0x06 (Continued) Bit Bit Name 0 LP_AN_ABLE 7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 20. ...
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... Link Code Word Page Received: This is a duplicate of the Page Received bit in the ANER register, but this bit will not be cleared upon a read of the PHYSTS register new Link Code Word Page has been received. Cleared on read of the ANER (address 0x06, bit 1). ...
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... Auto-Negotiation is disabled and there is a valid link. Link Status: This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be cleared upon a read of the PHYSTS regis- ter Valid link established (for either 10 or 100 Mb/s operation Link not established. ...
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... MII Interrupt Control Register (MICR) This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII Inter- rupt Status and Event Control Register (MISR) Table 22 ...
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MII Interrupt Status and Misc. Control Register (MISR) This register contains event status and enables for the interrupt function event has occurred since the last read of this register, the corresponding status bit will be set. If ...
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... FCSCNT[7:0] 7.2.5 Receiver Error Counter Register (RECR) This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY man- aged object class of Clause 30 of the IEEE 802.3u specification. Table 25. Receiver Error Counter Register (RECR), address 0x15 ...
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Mb/s PCS Configuration and Status Register (PCSR) Table 26. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 Bit Bit Name 15:13 RESERVED 12 RESERVED 11 RESERVED 10 TQ_EN 9 SD FORCE PMA 8 SD_OPTION 7 DESC_TIME ...
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RMII and Bypass Register (RBR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 27. RMII and Bypass Register (RBR), addresses 0x17 Bit Bit Name 15:6 RESERVED 5 RMII_MODE ...
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... PHY Control Register (PHYCR) Table 29. PHY Control Register (PHYCR), address 0x19 Bit Bit Name 15 MDIX_EN 14 FORCE_MDIX 13 PAUSE_RX 12 PAUSE_TX 11 BIST_FE 10 PSR_15 9 BIST_STATUS 8 BIST_START 7 BP_STRETCH Default Strap, RW Auto-MDIX Enable Enable Auto-neg Auto-MDIX capability Disable Auto-neg Auto-MDIX capability. The Auto-MDIX algorithm requires that the Auto-Negotiation En- able bit in the BMCR register to be set ...
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... RW In half-duplex mode, default 10BASE-T operation loops Transmit data to the Receive data in addition to transmitting the data on the physical medium. This is for consistency with earlier 10BASE2 and 10BASE5 implementations which used a shared medium. Setting this bit disables the loopback function. This bit does not affect loopback due to setting BMCR[14]. ...
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... Forced Good 10Mb Link Normal Link Status. RESERVED: Must be zero. 10Mb Polarity Status: This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS register Inverted Polarity detected Correct Polarity detected. ...
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... Allows continuous pseudo random data transmission without any break in transmission. This can be used for transmit VOD testing. This is used in conjunction with the BIST controls in the PHYCR Register (0x19h). For 10Mb operation, jabber function must be dis- abled, bit 0 of the 10BTSCR (0x1Ah), JABBER_DIS = 1. ...
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... Default 0, RW Energy Detect Enable: Allow Energy Detect Mode. When Energy Detect is enabled and Auto-Negotiation is disabled via the BMCR register, Auto-MDIX should be disabled via the PHY- CR register Energy Detect Automatic Power Up: Automatically begin power up sequence when Energy Detect Data Threshold value (EDCR[3:0]) is reached. Alternatively, device could be powered up manually using the ED_MAN bit (ECDR[12]) ...
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Electrical Specifications Note: All parameters are guaranteed by test, statistical analysis or design. Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature (T ) STG Max ...
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Symbol Pin Types Parameter SD PMD Input 100BASE-TX THoff Pair Signal detect turn- off threshold V PMD Input 10BASE-T Re- TH1 Pair ceive Threshold I Supply 100BASE-TX dd100 (Full Duplex) I Supply 10BASE-T dd10 (Full Duplex) I Supply Power Down ...
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AC Specs 8.2.1 Power Up Timing Vcc X1 clock Hardware RESET_N MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T2.1.1 Post Power Up Stabilization time prior to MDC preamble for register accesses ...
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Reset Timing Vcc X1 clock Hardware RESET_N MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T2.2.1 Post RESET Stabilization time prior to MDC preamble for reg- ister accesses T2.2.2 Hardware Configuration Latch- ...
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MII Serial Management Timing MDC MDIO (output) MDC MDIO (input) Parameter Description T2.3.1 MDC to MDIO (Output) Delay Time T2.3.2 MDIO (Input) to MDC Setup Time T2.3.3 MDIO (Input) to MDC Hold Time T2.3.4 MDC Frequency 8.2.4 100 Mb/s ...
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Mb/s MII Receive Timing RX_CLK T2.5.2 RXD[3:0] RX_DV RX_ER Parameter Description T2.5.1 RX_CLK High/Low Time T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode Note: RX_CLK may be held low or high for a longer period ...
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Transmit Packet Deassertion Timing TX_CLK TX_EN TXD PMD Output Pair Parameter Description T2.7.1 TX_CLK to PMD Output Pair Deassertion Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deasser- ...
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Transmit Timing (t +1 rise PMD Output Pair T2.8.2 PMD Output Pair eye pattern Parameter Description T2.8.1 100 Mb/s PMD Output Pair t and t F 100 Mb/s t and t Mismatch R F T2.8.2 100 Mb/s PMD ...
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Receive Packet Latency Timing PMD Input Pair T2.9.1 CRS RXD[3:0] RX_DV RX_ER Parameter Description T2.9.1 Carrier Sense ON Delay T2.9.2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the first bit ...
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Mb/s MII Transmit Timing T2.11.1 TX_CLK TXD[3:0] TX_EN Parameter Description T2.11.1 TX_CLK High/Low Time T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise Note: An attached Mac should drive the transmit ...
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Mb/s Serial Mode Transmit Timing TX_CLK TXD[0] TX_EN Parameter Description T2.13.1 TX_CLK High Time T2.13.2 TX_CLK Low Time T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 8.2.14 10 Mb/s Serial ...
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Transmit Timing (Start of Packet) TX_CLK TX_EN TXD PMD Output Pair Parameter Description T2.15.1 Transmit Output Delay from the Falling Edge of TX_CLK T2.15.2 Transmit Output Delay from the Rising Edge of TX_CLK Note: 1 bit time = ...
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Receive Timing (Start of Packet TPRD T2.17.1 CRS RX_CLK T2.17.2 RX_DV 0000 RXD[3:0] Parameter Description T2.17.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) T2.17.2 RX_DV Latency T2.17.3 Receive Data Latency Note: 10BASE-T RX_DV ...
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Mb/s Heartbeat Timing TX_EN TX_CLK COL Parameter Description T2.19.1 CD Heartbeat Delay T2.19.2 CD Heartbeat Duration 8.2.20 10 Mb/s Jabber Timing TXE PMD Output Pair COL Parameter Description T2.20.1 Jabber Activation Time T2.20.2 Jabber Deactivation Time T2.19.2 T2.19.1 ...
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Normal Link Pulse Timing Normal Link Pulse(s) Parameter Description T2.21.1 Pulse Width T2.21.2 Pulse Period Note: These specifications represent transmit timings. 8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing T2.22.1 Fast Link Pulse(s) Parameter Description T2.22.1 Clock, Data Pulse ...
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Signal Detect Timing PMD Input Pair T2.23.1 SD+ internal Parameter Description T2.23.1 SD Internal Turn-on Time T2.23.2 SD Internal Turn-off Time Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. 8.2.24 100 Mb/s Internal Loopback ...
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Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] Parameter Description T2.25.1 TX_EN to RX_DV Loopback Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. www.national.com T2.25.1 Notes 10 Mb/s ...
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RMII Transmit Timing X1 TXD[1:0] TX_EN PMD Output Pair Parameter Description T2.26.1 X1 Clock Period T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising T2.26.4 X1 Clock to PMD Output Pair Latency ...
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RMII Receive Timing PMD Input Pair IDLE (J/K) X1 T2.27.3 RX_DV CRS_DV RXD[1:0] RX_ER Parameter Description T2.27.1 X1 Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV, and RX_ER output delay from X1 rising T2.27.3 CRS ON delay T2.27.4 CRS OFF delay ...
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... Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) H/W or S/W Reset (with PHYAD = 00000) MODE Parameter Description T2.28.1 From software clear of bit 10 in the BMCR register to the transi- tion from Isolate to Normal Mode T2.28.2 From Deassertion of S/W or H/W ...
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Mb TX_CLK Timing X1 TX_CLK Parameter Description T2.30 TX_CLK delay Note TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data. www.national.com ...
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Notes: 83 www.national.com ...
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