SI3210M-FTR Silicon Laboratories Inc, SI3210M-FTR Datasheet
SI3210M-FTR
Specifications of SI3210M-FTR
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SI3210M-FTR Summary of contents
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... CMOS integrated circuit. The integrated battery supply continuously adapts its output voltage to minimize power and enables the entire solution to be powered from a single 3.3 V (Si3210M/Si3211M only supply. The ProSLIC controls the phone line through Silicon Labs’ Si3201 Linefeed Interface Chip. ...
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Si3210/Si3211 2 Rev. 1.45 ...
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... Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 4.1. DTMF Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 4.2. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.3. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.5. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 5. Pin Descriptions: Si3210/ 125 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9 ...
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Si3210/Si3211 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage 2 Operating Temperature Range Storage Temperature Range TSSOP-38 Thermal Resistance, Typical QFN-38 Thermal Resistance, Typical 2 ...
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Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3210/11 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply ...
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Si3210/Si3211 Table 3. AC Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Gain Variation with Temperature Gain Variation with Supply 2-Wire ...
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Figure 1. Transmit and Receive Path SNDR Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 2. Overload Compression Performance Rev. 1.45 Si3210/Si3211 Acceptable Region 4 ...
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Si3210/Si3211 Figure 3. Transmit Path Frequency Response 8 Typical Response Typical Response Rev. 1.45 ...
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Figure 4. Receive Path Frequency Response Rev. 1.45 Si3210/Si3211 9 ...
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Si3210/Si3211 Figure 5. Transmit Group Delay Distortion Figure 6. Receive Group Delay Distortion 10 Rev. 1.45 ...
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Table 4. Linefeed Characteristics ( 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol Loop Resistance Range* R LOOP DC Loop Current Accuracy DC Open ...
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Si3210/Si3211 Table 5. Monitor ADC Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity ...
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Table 8. Power Supply Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Power Supply Current Analog and Digital ...
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Si3210/Si3211 Table 9. Switching Characteristics (General Inputs 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width ...
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Table 10. Switching Characteristics (SPI 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, ...
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Si3210/Si3211 Table 11. Switching Characteristics—PCM Highway Serial Interface V = 3. °C for K-Grade, – °C for B-Grade Parameter PCLK Frequency PCLK Duty Cycle Tolerance PCLK-to-FSYNC Jitter ...
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... Only one component per system needed. 3. All circuit ground should have a single-point connection to the ground plane. 4. Si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. 5. Pin numbers for TSSOP shown. Figure 9. Si3210/Si3210M Application Circuit Using Si3201 R1 200k 15 STIPDC 20 STIPAC C24 0.1 ...
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... Si3210/Si3211 Table 12. Si3210/Si3210M + Si3201 External Component Values Component(s) 10 µ Ceramic Low Leakage C1,C2 Electrolytic, ±20% C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C15,C16,C17,C24 0.1 µ Y5V, ±20% C18,C19 4.7 µF, ceramic X7R, ±20% C26 0.1 µF, 100 V, X7R, ±20% C30,C31 10 µ ...
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SDCH 1 R19 Note 1 1 R20 SDCL C10 R16 0.1 µF 200 DCFF 2N2222 DCDRV Notes: 1. Values and configurations for these components can be derived from “AN45: Design Guide for the Si3210 DC-DC Converter” or Table 21. 2. ...
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Si3210/Si3211 Table 13. Si3210 BJT/Inductor DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C10 0.1 µ X7R, ±20% C14* 0.1 µF, X7R, ±20% C25* 10 µF, Electrolytic, ±20% 200 , 1/10 W, ±5% R16 ...
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... Values and configurations for these components can be derived from AN45 or Table 20. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 11. Si3210M MOSFET/Transformer DC-DC Converter Circuit Table 14. Si3210M MOSFET/Transformer DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C14* 0.1 µ ...
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Si3210/Si3211 1 TIP TIP Protection Circuit RING RING C9 0.1 µF GND Notes: 1. Only one component per system needed. 2. All circuit grounds should have a single- point connection to the ground ...
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Table 15. Si3211 + Si3201 External Component Values Component(s) C1,C2 10 µ Ceramic Low-Leakage Electrolytic, ±20% C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C9 0.1 µF, 100 V, ...
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... Optional components to improve idle channel noise. 5. The trace resistance between R6 and C26 should equal the trace resistance between R 7 and C26. 6. Pin numbers for TSSOP shown. Figure 13. Si3210/Si3210M Typical Application Circuit Using Discrete Components 24 R1 200k 15 GND STIPDC ...
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... Table 16. Si3210/Si3210M External Component Values—Discrete Solution Component(s) Value 10 µ Ceramic Low-Leakage C1,C2 Electrolytic, 20% 220 nF, 100 V, X7R, 20% C3,C4 22 nF, 100 V, X7R, 20% C5,C6 220 nF X7R, 20% C7,C8 0.1 µ Y5V, 20% C15,C16,C17 0.1 µF, 100 V, X7R, 20% C26 C30,C31 10 µ ...
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Si3210/Si3211 Q1 5401 R10 10 TIP Q6 5551 C8 C5 220nF 22nF Protection Circuit R6 C6 80.6 22nF RING C26 0.1 µF Notes: 1. Only one component per system needed. 2. All circuit grounds should have a single-point connection to ...
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Table 17. Si3211 External Component Values—Discrete Solution Component(s) 10 µ Ceramic Low Leakage C1,C2 Electrolytic, 20% 220 nF, 100 V, X7R, 20% C3,C4 22 nF, 100 V, X7R, 20% C5,C6 220 nF X7R, ...
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... V, X7R, 20% C7,C8 3.0 k, 1/10 W, 5% R23,R24 The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5 and Q6. For this optional subcircuit, C7 and C8 differ in Table 19. Component Value Selection for Si3210/Si3210M Component 1/ resistor R28 For V DD For V ...
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... Table 20. Component Value Selection Examples for Si3210M MOSFET/Transformer DC-DC Converter VDC Maximum Ringing Load/Loop Resistance 3 REN/117 3 REN/117 5 REN/117 REN/117 Note: There are other system and software conditions that influence component value selection. Refer to “AN45: Design Guide for the Si3210 DC-DC Converter” for detailed guidance. ...
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... The ProSLIC has programmable constant voltage and constant current zones as shown in Figure 16. Open- circuit TIP-to-RING voltage (V voltage zone and is programmable from 94 1.5 V steps. The loop current limit (I constant current zone and is programmable from steps. The ProSLIC has an inherent ) of 160 . dc output resistance ( (V) ...
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... See Calibration" on page 36 for details. 2.1.3. Linefeed Operation States The ProSLIC linefeed has eight states of operation as shown in Table 23. The state of operation is controlled using the Linefeed Control register (direct Register 64). The open state turns off all currents into the external bipolar transistors and can be used in the presence of fault conditions on the line and to generate Open Switch Intervals (OSIs) ...
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... A/D D/A AC Control AC Sense Control Loop TIP or RING Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown) Table 23. ProSLIC Linefeed Operations LF[2:0]* Linefeed State 000 Open 001 Forward Active 010 Forward On-Hook Transmission 011 TIP Open 100 Ringing ...
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... Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. 2.1.5. Power Monitoring and Line Fault Detection In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each external bipolar transistor ...
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... Power Alarm Interrupt Enable Power Alarm Automatic/Manual Detect *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). ...
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... Loop Closure Transition Detection A loop closure transition event signals that the terminal equipment has gone from on-hook to off-hook or from off-hook to on-hook; detection occurs while the ProSLIC linefeed is in its on-hook transmission or active states. The ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter ...
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... DCDRV and DCFF pins to switch Q7 on and off. DCDRV controls Q7 through NPN BJT Q8. DCFF is ac-coupled to Q7 through capacitor C10 to assist R16 in turning off Q7. Therefore, DCFF must have opposite polarity to DCDRV, and the Si3210 (not Si3210M) must be used. Rev. 1.45 DCFF Signal ...
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... T1 specified in “AN45: Design Guide for the Si3210 DC-DC Converter” and includes several taps on the primary side to facilitate a wide range of input voltages. The Si3210M version of the Si3210 must be used for the application circuit depicted in Figure 11 because the DCFF pin is used to drive M1 directly and, therefore, must be the same polarity as DCDRV. DCDRV is not used in this circuit option ...
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... Low Battery Voltage—V BATL V OV Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). 38 TRACK = 0 mode is desired since the regulator output ...
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... This option is enabled by setting DCFIL = 1 (direct Register 108, bit 1). 2.2.6. DC-DC Converter During Ringing When the ProSLIC enters the ringing state, it requires voltages well above those used in the active mode. The voltage to be generated and regulated by the dc-dc converter during a ringing burst is set using the V register (direct Register 74) ...
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Si3210/Si3211 8 kHz Clock OnE Zero 16-Bit Cross OAT Modulo Logic Expire Counter OIT Expire OATn OATnE OITn OITnE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Figure 20. Simplified Tone Generator ...
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The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the ...
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... Both sinusoidal and trapezoidal ringing waveforms are supported, and the trapezoidal crest factor is programmable. Ringing signals peak or more can be generated, enabling the ProSLIC to drive a 5 REN (1380 µF) ringer load across loop lengths of 2000 feet (160 ) or more. gives detailed 2 ...
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... Ringing initial phase Common Mode Bias Adjust During Ringing Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31) ...
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... V . ROFF V TIP-RING V ROFF T=1/freq t RISE Figure 22. Trapezoidal Ringing Waveform To configure the ProSLIC for trapezoidal ringing, the user should follow the same basic procedure as in the Sinusoidal Ringing section, but using the following equations: 1 RNGY = -- - Period 2 ...
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... Register 79. LCS data is processed by the input signal processor when the ProSLIC is in the ringing state as indicated by the Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low-pass filter that removes unwanted ac signal components before threshold detection. ...
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... Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31) ...
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... Pulse Metering Inactive Timer Pulse Metering Control Status and control registers Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped directly. An indirect register is one that is accessed using the indirect access registers (direct registers 28 through 31). ...
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... Si3210/Si3211 2.7. Audio Path Unlike traditional SLICs, the codec function is integrated into the ProSLIC. The 16-bit codec offers programmable gain/attenuation blocks and several loopback modes. The signal path block diagram is shown in Figure 25. 2.7.1. Transmit Path In the transmit path, the analog signal fed by the ...
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Si3210/Si3211 Rev. 1.45 49 ...
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... If desired, the transhybrid balance can also be disabled using the appropriate register setting. 2.7.5. Loopback Testing Four loopback test options are available in the ProSLIC: The full analog loopback (ALM2) tests almost all the circuitry of both the transmit and receive paths. The ...
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... The PLL clock synthesizer settles very quickly following powerup. However, the settling time depends on the PCLK frequency, and it can be approximated by the following equation: T ---------------- - = SETTLE F 2.10. Interrupt Logic The ProSLIC is capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected (XAC), and a ...
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... SDI is a “don’t care” during the data portion of read operations. During write operations, data is driven into the ProSLIC via the SDI pin MSB first. The SDO pin will remain high impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the rising edge ...
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SCLK CS SDI SDO SCLK CS SDI SDO High Impedance Don't Care High Impedance Figure 26. Serial Write 8-Bit Mode Don't Care ...
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Si3210/Si3211 SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – ...
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... GCI mode.) Timeslots for data transmission and reception are independently configured using the TXS and RXS registers. By setting the correct starting point of the data, the ProSLIC can be configured to support long FSYNC and short FSYNC variants as well as IDL2 8-bit, 10-bit, B1 and B2 channel time slots. DTX data is high-impedance except for the duration of the 8- bit PCM transmit ...
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... DTX HI-Z Figure 32. GCI Example, Timeslot 1 (TXS/RXS = 0) 2.13. Companding The ProSLIC supports both µ-255 Law and A-Law companding formats in addition to linear data. These 8- bit companding schemes follow a segmented curve formatted as sign bit, three chord bits, and four step bits. µ-255 Law is more commonly used in North America and Japan, while A-Law is primarily used in Europe ...
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Table 34. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Si3210/Si3211 Table 35. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 ...
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... PCMT GCI TRI TXS[9:8] RXS[9: DIO2 DIO1 PD2 PD1 ALM2 DLM ALM1 ATX[1:0] ARX[1:0] TISE TISS[2:0] HYBA[2:0] MOF BIASOF SLICOF DACON GMM GMON O2IP O2AP O1IP O1AP Q2AP Q1AP LCIP RTIP CMCP INDP DTMFP O2IE O2AE O1IE O1AE Q2AE Q1AE LCIE ...
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Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name 28 Indirect Data Access— Low Byte 29 Indirect Data Access— High Byte 30 Indirect Address 31 Indirect Address Status 32 Oscillator 1 Control 33 Oscillator 2 Control 34 Ringing Oscillator Control ...
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... Power Monitor Pointer 77 Line Power Output Monitor 78 Loop Voltage Sense Notes: 1. Si3211 only. 2. Si3210 only. Bit 7 Bit 6 Bit 5 Bit 4 PIT[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] SLIC LCD[7:0] LFS[2:0] SQH CBY ETBE 2 VOV MNCM MNDIF SPDS VSGN PWROM[7:0] LVSP Rev. 1.45 Si3210/Si3211 Bit 3 Bit 2 ...
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Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name 79 Loop Current Sense 80 TIP Voltage Sense 81 RING Voltage Sense 82 Battery Voltage Sense 1 83 Battery Voltage Sense 2 84 Transistor 1 Current Sense 85 Transistor 2 Current ...
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Table 36. Direct Register Summary (Continued) Register Name 102 Current Limit Calibration Result 103 Monitor ADC Offset Calibration Result 104 Analog DAC/ADC Offset 105 DAC Offset Calibration Result 106 Common Mode Balance Calibration Result 107 DC Peak Current Calibration Result ...
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... Enable SPI daisy chain mode. 6 SPIM SPI Mode Causes SDO to tri-state on rising edge of SCLK of LSB Normal operation; SDO tri-states on rising edge of CS. 5:4 PNI[1:0] Part Number Identification Si3210 01 = Si3211 10 = Unused 11 = Si3210M 3:0 RNI[3:0] Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc PNI[1:0] R Function Rev ...
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Register 1. PCM Mode Select Bit D7 D6 Name PNI2 Type Reset settings = 0000_1000 Bit Name 7 PNI2 Part Number Identification Si3210/11 family Si3215/16 family. 6 Reserved Read returns zero. 5 PCME PCM Enable. ...
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Si3210/Si3211 Register 2. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data trans- mission ...
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Register 5. PCM Receive Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[9:8] PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC ...
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Si3210/Si3211 Bit Name 7:5 Reserved Read returns zero. 4 DOUT DOUT Pin Output Data (Si3211 only DOUT pin driven low DOUT pin driven high. Si3210 = Reserved. 3 DIO2 DIO2 Pin Input/Output Direction (Si3211 only). 0 ...
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Register 8. Audio Path Loopback Control Bit D7 D6 Name Type Reset settings = 0000_0010 Bit Name 7:3 Reserved Read returns zero. 2 ALM2 Analog Loopback Mode 2. (See Figure 25 on page 49 Full analog loopback mode ...
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Si3210/Si3211 Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHDF HPF ...
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Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off ...
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Si3210/Si3211 Register 11. Hybrid Control Bit D7 D6 Name Type Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 ...
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... Reserved Read returns zero. 1 BIASOF DC Bias Power-Off Control Automatic power control Override automatic control and force dc bias circuitry off. 0 SLICOF SLIC Power-Off Control Automatic power control Override automatic control and force SLIC circuitry off. Si3210 PMON DCOF MOF R/W R/W R/W ...
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Si3210/Si3211 Register 15. Powerdown Control 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual power ...
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Register 18. Interrupt Status 1 Bit D7 D6 Name PMIP PMAP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIP Pulse Metering Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Si3210/Si3211 Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCP Common Mode Calibration Error Interrupt. This bit is set when off-hook/on-hook status changes during the common mode ...
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Si3210/Si3211 Register 21. Interrupt Enable 1 Bit D7 D6 Name PMIE PMAE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIE Pulse Metering Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 6 PMAE Pulse ...
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Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE Power Alarm Q5 ...
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Si3210/Si3211 Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCE Common Mode Calibration Error Interrupt Enable Interrupt masked Interrupt enabled. 1 INDE ...
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Register 24. DTMF Decode Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 VAL DTMF Valid Digit Decoded Not currently detecting digit Currently detecting digit. 3:0 DIG[3:0] ...
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Si3210/Si3211 Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA ...
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Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register ...
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Si3210/Si3211 Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 REL Oscillator ...
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Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. 5 ...
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Si3210/Si3211 Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 Reserved ...
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Register 35. Pulse Metering Oscillator Control Bit D7 D6 Name PSTAT Type R Reset settings = 0000_0000 Bit Name 7 PSTAT Pulse Metering Signal Status Output signal inactive Output signal active. 6:5 Reserved Read returns zero. ...
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Si3210/Si3211 Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[15:8] Oscillator 1 Active Timer. Register 38. Oscillator 1 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = ...
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Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT2[7:0] Oscillator 2 Active Timer. LSB = 125 µs Register 41. Oscillator 2 Active Timer—High Byte Bit D7 D6 Name Type ...
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Si3210/Si3211 Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[15:8] Oscillator 2 Inactive Timer. Register 44. Pulse Metering Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings ...
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Register 46. Pulse Metering Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 PIT[7:0] Pulse Metering Inactive Timer. LSB = 125 µs Register 47. Pulse Metering Oscillator Inactive Timer—High Byte Bit D7 D6 ...
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Si3210/Si3211 Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 ...
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Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, ...
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Si3210/Si3211 Register 64. Linefeed Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real-time linefeed state. Automatic operations may cause actual linefeed state ...
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Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. 5 ...
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Si3210/Si3211 Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit D7 D6 Name Type Reset settings = 0000_0110 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. (Si3210 only; See ...
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Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which TIP (forward) ...
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Si3210/Si3211 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the real-time output of ...
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Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady ...
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Si3210/Si3211 Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage ...
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Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. V equal to VBATL. ...
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Si3210/Si3211 Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of ...
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Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (V ...
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Si3210/Si3211 Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the real-time voltage at TIP with respect to ground. The range (0x00) ...
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Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the real-time voltage ground. The ...
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Si3210/Si3211 Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the real-time current through Q3. The range (0x00) to 9.59 ...
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Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the real-time current through Q6. The range (0x00) to 80.58 mA ...
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... This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3210 are offered to support the two relationships DCFF pin polarity is opposite of DCDRV pin (Si3210 DCFF pin polarity is same as DCDRV pin (Si3210M). Si3211 = Reserved. 4:0 DCTOF[4:0] DC-DC Converter Minimum Off Time (Si3210 only) ...
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Register 94. DC-DC Converter PWM Pulse Width Bit D7 D6 Name Type Reset settings = 0000_0000 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width (Si3210 only). Pulse width of DCDRV is ...
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Si3210/Si3211 Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 ...
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Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1111 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or ...
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Si3210/Si3211 Register 99. TIP Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMT[4:0] Gain Mismatch of IE Tracking Loop for TIP Current. Register 100. Differential Loop Current ...
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Register 102. Current Limit Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:5 Reserved Read returns zero. 3:0 CALGIL[3:0] Current Limit Calibration Result. Register 103. Monitor ADC Offset Calibration Result Bit D7 D6 Name CALMG1[3:0] ...
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Si3210/Si3211 Register 105. DAC Offset Calibration Result Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DACOF[7:0] DAC Offset Calibration Result. Register 106. Common Mode Balance Calibration Result Bit D7 D6 Name Type Reset settings = 0010_0000 ...
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Register 108. Enhancement Enable Note: The Enhancement Enable register and associated features are available in silicon revisions C and later. Bit D7 D6 Name ILIMEN FSKEN Type R/W R/W Reset settings = 0000_0000 Bit D7 D6 Name ILIMEN FSKEN Type ...
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Si3210/Si3211 Bit Name 4 ZSEXT Impedance Internal Reference Resistor Disable. When enabled, this bit removes the internal reference resistor used to synthesize ac impedances for 600 + 2.1 µF and 900 + 2.16 µF so that an external resistor reference ...
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Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. ...
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Si3210/Si3211 Table 38. DTMF Indirect Registers Description Addr. 0 DTMF Row 0 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of power in row 0 to total ...
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Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in 2s- complement format. Note: The values of all indirect registers are undefined follow- ing the reset ...
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Si3210/Si3211 Table 40. Oscillator Indirect Registers Description Addr. Oscillator 1 Frequency Coefficient. 13 Sets tone generator 1 frequency. Oscillator 1 Amplitude Register. 14 Sets tone generator 1 signal amplitude. Oscillator 1 Initial Phase Register. 15 Sets initial phase of tone ...
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Digital Programmable Gain/Attenua- tion See functional description sections programmable gain/attenuation for computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined follow- ing the reset state. Shaded areas denote bits ...
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... All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined follow- ing the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes. Table 43. SLIC Control Indirect Registers Summary Addr. D15 D14 D13 ...
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... Table 44. SLIC Control Indirect Registers Description Addr. 28 Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hys- teresis is enabled (direct Register 108, bit 0). The range is 0– 1.27 mA steps. 29 Ring Trip Threshold. Ring trip detection threshold during ringing. ...
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Si3210/Si3211 4.5. FSK Control For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and ...
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Pin Descriptions: Si3210/11 QFN DTX FSYNC 2 RESET 3 SDCH/DIO1 4 SDCL/DIO2 DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC ...
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... SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. Component Reference Ground. SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. TIP Sense. Analog current input used to sense voltage on the TIP lead. RING Sense. Analog current input used to sense voltage on the RING lead. ...
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QFN TSSOP Name Pin # Pin # 23 27 VDDA2 Analog Supply Voltage. Analog power supply for internal analog circuitry ITIPP Positive TIP Current Control. Analog current output driving Q1 ITIPN Negative TIP Current Control. Analog ...
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Si3210/Si3211 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O ...
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... Si3210-E-FM ProSLIC Si3210-E-GM ProSLIC Si3210M-E-FM ProSLIC Si3210M-E-GM ProSLIC Si3210-KT ProSLIC Si3210-BT ProSLIC Si3210-FT ProSLIC Si3210-GT ProSLIC Si3210M-KT ProSLIC Si3210M-BT ProSLIC Si3210M-FT ProSLIC Si3210M-GT ProSLIC Si3211-KT ProSLIC Si3211-BT ProSLIC Si3211-E-FT ProSLIC Si3211-E-GT ProSLIC Si3211-E-FM ProSLIC Si3211-E-GM ProSLIC Si3201-KS Linefeed Interface Si3201-BS Linefeed ...
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... Eval Board, Daughter Card Si3210-QFN Eval Board, Daughter Card Si3210-TSSOP Eval Board, Daughter Card Si3210-TSSOP Eval Board, Daughter Card Si3210M-TSSOP Eval Board, Daughter Card Si3210M-TSSOP Eval Board, Daughter Card Si3211-TSSOP Eval Board, Daughter Card Rev. 1.45 Linefeed Interface Discrete Si3201 Discrete ...
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Package Outline: 38-Pin QFN Figure 33 illustrates the package details for the Si321x. Table 48 lists the values for the dimensions shown in the illustration. Figure 33. 38-Pin Quad Flat No-Lead Package (QFN) Table 48. Package Diagram Dimensions Symbol ...
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Si3210/Si3211 9. Package Outline: 38-Pin TSSOP Figure 34 illustrates the package details for the Si321x. Table 49 lists the values for the dimensions shown in the illustration. Figure 34. 38-Pin Thin Shrink Small Outline Package (TSSOP) Table 49. Package Diagram ...
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Package Outline: 16-Pin ESOIC Figure 35 illustrates the package details for the Si3201. Table 50 lists the values for the dimensions shown in the illustration. Figure 35. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package Si3210/Si3211 Rev. 1.45 ...
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Si3210/Si3211 Table 50. Package Diagram Dimensions Symbol aaa bbb ccc ddd 134 Millimeters Min A — A1 0.00 A2 1.25 b 0.31 c 0.17 D 9.90 BSC D1 3.45 E 6.00 BSC E1 3.90 BSC E2 2.20 e 1.27 BSC ...
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... Updated to include product revision designator. “Lead-Free” changed to “Lead-Free and RoHS- Compliant” Figure 9, “Si3210/Si3210M Application Circuit Using Si3201,” on page 17. Added additional decoupling components to VDDA1, VDDA2, and VDDD. Figure 12, “Si3211 Typical Application Circuit Using Si3201,” ...
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Si3210/Si3211 Added Note 1. Updated Table 16. Changed current rating 150 mA. Corrected missing reference to R5. Added new row for R26 and changed the value to 10 k. Added title for ...
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N : OTES Si3210/Si3211 Rev. 1.45 137 ...
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