IDT82V1671J IDT, Integrated Device Technology Inc, IDT82V1671J Datasheet
IDT82V1671J
Specifications of IDT82V1671J
Available stocks
Related parts for IDT82V1671J
IDT82V1671J Summary of contents
Page 1
... DESCRIPTION The RSLIC-CODEC chipset is comprised of one four-channel programmable PCM CODEC (IDT82V1074) and four single-channel ringing SLICs (IDT82V1671 / IDT82V1671A). The chipset provides a total solution for line card designs. In addition to providing a complete software programmable solution for BORSCHT, additional functions such as FSK generator, Universal Tone Detection (UTD) unit, tone ...
Page 2
... RSLIC & CODEC CHIPSET RSLIC FUNCTIONAL BLOCK DIAGRAM TIS TIP RING RIS RSP RSN VBL VBH VCM VDD Battery Switch Line Driver Ring Trip RT 2 IDT82V1671/IDT82V1671A, IDT82V1074 GND IL VL Sense VTDC IT VTAC Sense CA ACN ACP Input DCN Stage DCP CS Logic M1 Control ...
Page 3
... RSLIC & CODEC CHIPSET CODEC FUNCTIONAL BLOCK DIAGRAM Channel1 for AC Filter and A/D for AC VTAC1 ACP1 D/A and Filter for AC ACN1 4 I/Os SLIC Signaling CS1 Channel2 for AC Channel3 for AC Channel4 for AC PLL and Clock MCLK Generation M1 SLIC Interface M2 Control M3 MPI/GCI INT/INT ...
Page 4
... RSLIC & CODEC CHIPSET 1 Pin Configurations .............................................................................................................................................................................................9 1.1 RSLIC Pin Configuration ...........................................................................................................................................................................9 1.2 CODEC Pin Configuration .......................................................................................................................................................................10 2 Pin Descriptions...............................................................................................................................................................................................11 2.1 RSLIC Pin Description.............................................................................................................................................................................11 2.2 CODEC Pin Description ..........................................................................................................................................................................12 3 Functional Description ....................................................................................................................................................................................16 3.1 Functions Overview .................................................................................................................................................................................16 3.1.1 Basic Functions ..........................................................................................................................................................................16 3.1.2 Additional Functions ...................................................................................................................................................................16 3.1.3 Programmable Functions ...........................................................................................................................................................16 3.2 DC Feeding ...
Page 5
... Upstream C/I Channel Byte........................................................................................................................................55 4.2.4 GCI Monitor Transfer Protocol....................................................................................................................................................56 4.2.4.1 Monitor Channel Operation ........................................................................................................................................56 4.2.4.2 Monitor Handshake Procedure...................................................................................................................................56 4.3 Analog POTS Interface............................................................................................................................................................................58 4.4 RSLIC and CODEC Interface ..................................................................................................................................................................58 5 Programming....................................................................................................................................................................................................59 5.1 Overview..................................................................................................................................................................................................59 5.1.1 MPI Programming ......................................................................................................................................................................59 5.1.1.1 Broadcast Mode for MPI Programming ......................................................................................................................59 5.1.1.2 Identification Code for MPI Programming...................................................................................................................59 5 ...
Page 6
... Default State After Reset.........................................................................................................................................................................93 6.8.1 Power-On Reset and Hardware Reset.......................................................................................................................................93 6.8.2 Software Reset...........................................................................................................................................................................93 7 Electrical Characteristics ................................................................................................................................................................................94 7.1 RSLIC Electrical Characteristics..............................................................................................................................................................94 7.1.1 RSLIC Absolute Maximum Ratings ............................................................................................................................................94 7.1.2 RSLIC Recommended Operating Conditions.............................................................................................................................94 7.1.3 RSLIC Thermal Information........................................................................................................................................................94 7.1.4 RSLIC Power Consumption .......................................................................................................................................................94 7.2 CODEC Electrical Characteristics ...........................................................................................................................................................95 7.2.1 CODEC Absolute Maximum Ratings ...
Page 7
... RSLIC & CODEC CHIPSET Figure - 1 Line Circuit Functions Included in the RSLIC-CODEC Chipset ........................................................................................................ 16 Figure - 2 DC Feeding Zones ............................................................................................................................................................................ 17 Figure - 3 Constant Current Zone...................................................................................................................................................................... 17 Figure - 4 Resistive Zone................................................................................................................................................................................... 17 Figure - 5 Constant Voltage Zone...................................................................................................................................................................... 18 Figure - 6 DC Feeding Characteristics Configuration ........................................................................................................................................ 18 Figure - 7 DC Feeding Configuration Example for Short Loop Applications...................................................................................................... 18 Figure - 8 Signal Paths for AC Transmission ...
Page 8
... Local Register Addressing in MPI Mode ............................................................................................................................................60 Table - 22 Local Register Addressing in GCI Mode ............................................................................................................................................60 Table - 23 Coefficient RAM Mapping...................................................................................................................................................................62 Table - 24 Global Registers Mapping ..................................................................................................................................................................63 Table - 25 Local Registers Mapping....................................................................................................................................................................64 Table - 26 RSLIC Operating Mode ......................................................................................................................................................................89 Table - 27 Interrupt Source and Interrupt Mask...................................................................................................................................................91 Table - 28 External Components in Application Circuits ...................................................................................................................................105 LIST OF TABLES 8 IDT82V1671/IDT82V1671A, IDT82V1074 ...
Page 9
... RSLIC & CODEC CHIPSET 1 PIN CONFIGURATIONS 1.1 RSLIC PIN CONFIGURATION 5 VDD 6 AGND VCM 9 ACN 10 ACP 11 DCN IDT82V1671/IDT82V1671A, IDT82V1074 IDT82V1671 / IDT82V1671 IDT82V1671A 9 25 VCMB 24 RSP 23 RSN ...
Page 10
... RSLIC & CODEC CHIPSET 1.2 CODEC PIN CONFIGURATION 81 IO1_4 82 IO2_4 83 IO3_4 84 IO4_4 85 IOGND 86 IO1_3 IO2_3 87 IO3_3 88 IO4_3 89 90 VDDA4 91 RTIN4 VL4 92 93 VTDC4 VTAC4 94 95 AGND 96 DCP4 97 CA1_4 98 CA2_4 99 DCN4 ACP4 100 IDT82V1671/IDT82V1671A, IDT82V1074 IDT82V1074 10 50 IO1_1 49 IO2_1 48 IO3_1 47 IO4_1 46 IOGND ...
Page 11
... The logic level of the CS pin determines the direction of the M3 pin. See the description of the CS pin for details. Mode control input 2. This is a binary logic pin, together with M1 and M3, controlling the operating mode of the RSLIC. Mode control input 1. This is a binary logic pin, together with M2 and M3, controlling the operating mode of the RSLIC. ...
Page 12
... External capacitor connection. An external capacitor is connected between this pin and the DCN2 pin for filtering (Channel 2). IDT82V1671/IDT82V1671A, IDT82V1074 Description (0 V< CS1 < 0 the CODEC sends mode control data to the RSLIC1 through the (2.2 V< CS1 < 3 the CODEC receives the temperature information of the RSLIC1 through ±0.5 V tolerance ), no mode control data or temperature information is transferred between (0 V< ...
Page 13
... External capacitor connection. An external capacitor is connected between this pin and the DCN4 pin for filtering (Channel 4). IDT82V1671/IDT82V1671A, IDT82V1074 Description (0 V< CS3 < 0 the CODEC sends mode control data to the RSLIC3 through the (2.2 V< CS3 < 3 the CODEC receives the temperature information of the RSLIC3 through ±0.5 V tolerance ), no mode control data or temperature information is transferred between (0 V< ...
Page 14
... RSLIC & CODEC CHIPSET Name Type Pin Number RSLIC operating mode control output 1. The M1to M3 pins together with the CSn pin ( for Channel respectively determine the operating mode of the RSLIC connected to Channel n of the CODEC. Refer to the description of the CSn pin for details ...
Page 15
... RSLIC & CODEC CHIPSET Name Type Pin Number VDDB Power 16 +3.3 V bias power supply. VDDIO Power 78 Power supply for IO pins. 7, 14, 23, AGND Power Analog ground. 35, 95 DGND Power 58, 65 Digital ground. IOGND Power 46, 85 Ground for IO pins. IDT82V1671/IDT82V1671A, IDT82V1074 Description 15 ...
Page 16
... Tip Ring # RSLIC 4 Tip Figure - 1 Line Circuit Functions Included in the RSLIC-CODEC Chipset signals, test tones, dial tones etc. • FSK generator The chipset provides a built-in FSK generator for sending Caller ID information. • Universal Tone Detection (UTD) The chipset provides a built-in UTD unit per channel to detect ...
Page 17
... Analog telephones require a DC current in the off-hook state with AC voice signals in the transmit and receive directions superimposed. Thus, once the telephone has gone off-hook, the SLIC must supply a DC current to the subscriber line. The RSLIC-CODEC chipset provides a fully programmable DC feeding characteristic to meet the requirements of different applications ...
Page 18
... RSLIC & CODEC CHIPSET I TIP-RING R Figure - 5 Constant Voltage Zone 3.2.5 DC FEEDING CHARACTERISTICS CONFIGURATION The DC feeding characteristic is programmable. When the DC_FEED bit in register LREG5 is set to 1, the default DC feeding characteristic will be selected (see Figure - is typically for -24 V battery voltage application. When the DC_FEED bit is set to 0, the DC feeding characteristic is determined by the coefficients written in the Coe-RAM ...
Page 19
... RSLIC & CODEC CHIPSET Table - 1 lists the registers and the Coe-RAM locations used for DC feeding configuration. For more information about the Coe-RAM, please refer to “5.2.5 Addressing the Coe-RAM” on page 61 page 62. Table - 1 Registers and Coe-RAM Locations Used for DC Feeding Configuration Parameter ...
Page 20
... PCM highway. In the receive direction, the CODEC processes data received from the PCM highway and outputs a differential analog signal to the RSLIC via the ACP and ACN pins. The RSLIC then amplifies this signal and applies it to the subscriber line. ...
Page 21
... RSLIC & CODEC CHIPSET In the transmit path, the analog voltage from the RSLIC is first filtered by an anti-aliasing filter (AAF) and then is converted to a digital signal by a 1-bit sigma-delta modulator (SDM). The digital signal is down-sampled to an intermediate sample frequency to feed to the digital impedance matching filter (IMF) ...
Page 22
... Coefficient RAM Mapping. 3.3.2.2 Transhybrid Balance The RSLIC-CODEC chipset provides a traditional transhybrid balance filter (ECF) for each channel to improve 4-wire return loss performance. The ECF coefficient is programmable. If the ECF bit in register LREG4 is set to 1, the ECF filter is disabled. If the ECF bit is set to 0, the Transhybrid Balance Filter Coefficient in the Coe-RAM is used ...
Page 23
... In addition, the ring trip detection can be performed internally by programming the ring trip threshold. If internal ringing mode is selected, the RSLIC will be automatically switched to the higher battery (VBH) for ringing generation. The ringing signal generated by the CODEC is sent to the RSLIC via the DCP and V DROP DROP ...
Page 24
... Figure - 50 on page 105 shows an application circuit that use an external ringing signal. If the RSLIC is set to External Ringing mode (see details), the ringing signal from an external ring generator will be switched to the Tip/Ring lines through an external relay during ring burst period, and will be removed during ring pause period. ...
Page 25
... Tip/Ring lines. The measuring procedure is as follows (to understand the following descriptions, users should understand the level meter first): 1. Set the CODEC to ACTIVE mode and set the RSLIC to External Ringing mode (see 2. Select the RTIN as the input to the DC path of the CODEC (LREG9: LM_SEL[3:0] = 1100) ...
Page 26
... Table - 3 Registers and Coe-RAM Locations Used for External Ringing Mode Parameter MPI mode: bits ACTIVE, SCAN_EN and SM[2:0] CODEC and RSLIC Operating Mode in LREG6; Configuration GCI mode: bit ACTIVE in LREG6, bits SCAN_EN and SM[2:0] in downstream C/I channel byte ...
Page 27
... Active Sleep Standby Standby Note: The operating mode of the CODEC is set by register LREG6. The operating mode of the RSLIC is set by register LREG6 (for MPI mode) or downstream C/I channel byte. Refer to “6.1 Operating Modes” on page 87 • Active mode In this mode, both the RSLIC and the CODEC are active. The RSLIC senses the transversal current on the Ring and Tip lines, and feeds the corresponding voltage to the CODEC via VTDC pin ...
Page 28
... RSLIC & CODEC CHIPSET Off-hook/ Ground-key DB[3:0] Debounce Interval (0.125 ms − 2 ms) FS MCLK Figure - 14 Debounce Filter for Off-hook/Ground-key Detection Table - 5 Registers and Coe-RAM Locations Used for Off-hook Detection Parameter Register Bits/Coe-RAM Words Off-hook Indication Bits HK[3:0] in GREG26 Mask bit for HK[3:0] bits ...
Page 29
... In this case, the Tip line or the Ring line is switched to high impedance, the longitudinal current on the Ring or Tip line is sensed by the RSLIC and fed to the CODEC through the VL pin for testing. The longitudinal DC signal (which is taken as the ground-key criterion) is also filtered by the programmable debounce filter used in off- hook detection ...
Page 30
... The RSLIC-CODEC chipset provides an optimized FSK generator for sending Caller ID information. Different countries use different standards to send Caller ID information by FSK codes. The FSK modulation of the RSLIC-CODEC chipset is compatible with the most common standards: BELL 202 and ITU-T V.23. characteristics of these two standards. ...
Page 31
... RSLIC & CODEC CHIPSET Table - 8 FSK Modulation Characteristics Characteristic Mark (Logic 1) Space (Logic 0) Modulation Transmission Rate Data Format Generally, the transmission of the FSK signal starts with a Seizure Signal, which is a string of '01' pairs. Then a Mark Signal which is a string of ‘1’ follows. The Caller ID information comes after the Mark Signal ...
Page 32
... RSLIC & CODEC CHIPSET Table - 9 shows the configuration and control registers used for the FSK generator. Refer to Figure - 16 on page 33 programming flow chart for FSK generation. Table - 9 Registers and FSK-RAM Used for the FSK Generator Parameter Register Bits/FSK-RAM Flag Length Bits FSK_FL[7:0] (GREG19) ...
Page 33
... RSLIC & CODEC CHIPSET N Y Set Data Length (GREG20) Write CID data into FSK-RAM In GREG23: - Select a channel by setting bits FSK_CS[1:0]; - Select a standard by setting bit FSK_BS; - FSK_MAS = 0; - FSK_TS = 1 N FSK_TS = FSK_EN = 0 End Figure - 16 Recommended Programming Flow Chart for FSK Generation Start Read GREG23 ...
Page 34
... UNIVERSAL TONE DETECTION (UTD) 3.7.3.1 Introduction The RSLIC-CODEC chipset provides optimized solution not only for voice transmission, but for modem data transmission. The performance of the latter is becoming a key performance for the increasing internet access and other data applications. The chipset’s universal tone (fax/ modem tone) detection allows the use of modem-optimized filter for V ...
Page 35
... RSLIC & CODEC CHIPSET Tone UTD-OK UTD-OK Tone UTD-OK UTD-OK RBRKTime RTime RBRKTime RTime Figure - 18 Example of UTD Recognition Timing EBRKTime ETime EBRKTime ETime Figure - 19 Example of UTD Tone End Detection Timing 35 IDT82V1671/IDT82V1671A, IDT82V1074 ...
Page 36
... RSLIC & CODEC CHIPSET 3.7.3.3 UTD Programming Table - 10 shows the registers and Coe-RAM locations used for the UTD unit. The UTD unit can be enabled or disabled individually for each channel by the UTD_EN in register LREG8. The UTD_SRC bit in LREG8 determines whether the signal from transmit or receive path is detected ...
Page 37
... RSLIC & CODEC CHIPSET 3.8 THREE-PARTY CONFERENCE 3.8.1 INTRODUCTION The RSLIC-CODEC chipset provides a three-party conference facility on the PCM interface in MPI mode only. With this facility, either an external three-party conference or an internal three-party conference can be held without additional hardware. Figure - 20 shows the conference block diagram. When an external ...
Page 38
... RSLIC & CODEC CHIPSET Table - 11 Conference Mode Configuration Bits P_DOWN CONF_EN Mode (LREG6) (GREG7) PCM Off 1 0 PCM Active 0 0 External Conference 1 0 External Conference PCM Active Internal Conference 0 1 • PCM Off When the chipset is just reset the power down state, no data is transferred via the PCM highways ...
Page 39
... RSLIC & CODEC CHIPSET NOTES: In Table - 11 and Table - 12: 1. The ‘P_DOWN’ bit (in register LREG6) is used to power down the corresponding channel of the CODEC: P_DOWN = 1, power down; P_DOWN = 0, power on. 2. The ‘L_CODE’ bit (in register GREG3) is used to select the PCM data format: L_CODE = 1, linear code; L_CODE = 0, A/µ-law compressed code. ...
Page 40
... Traditional line cards solutions usually need external relays and test equipment to accomplish line tests. The RSLIC-CODEC chipset provides integrated test and diagnosis functions (ITDF) that can monitor and diagnose line faults and line card device failures without test relays or test equipment ...
Page 41
... RSLIC & CODEC CHIPSET LM_N = 1: the coefficient in the ROM is used for the notch filter; LM_B = 0: the coefficient in the Coe-RAM is used for the bandpass filter; LM_B = 1: the coefficient in the ROM is used for the bandpass filter; The center frequency of the notch/bandpass filter is programmable ...
Page 42
... RSLIC & CODEC CHIPSET 3.9.4.3 Level Meter Integrator An integrator is used to accumulate and sum up the signal values over a preset period. The accumulation period (count number) is programmable from 0 to 255.875 ms in steps of 0.125 ms, by the bits LM_CN[10:0] in registers GREG15 and GREG16. The integrator can be configured to run once or continuously by the LM_ONCE bit in GREG16: LM_ONCE = 0: integrator runs continuously ...
Page 43
... RSLIC & CODEC CHIPSET In both continuous and single modes, the level meter result LM is sent to registers GREG17 & GREG18 after every integration period. To calculate the measured signal level, a factor LM LM Value LM ---------------------- - = Result 32768 The number of samples N for the integrator is calculated by: ...
Page 44
... RSLIC & CODEC CHIPSET Table - 17 sums up the registers and Coe-RAM locations used for the level meter. Table - 17 Registers and Coe-RAM Locations Used for the Level Meter Parameter Register Bits/Coe-RAM Words Level meter channel selection LM_CS[1:0] bits in GREG16 LM_SRC and DC_SRC bits in LREG8 ...
Page 45
... The RSLIC must be set to Normal Active mode when measuring the leakage current Tip/Ring. • The RSLIC must be set to Tip Open mode when measuring the leakage current Ring/GND. • The RSLIC must be set to Ring Open mode when measuring the leakage current Tip/GND. • ...
Page 46
... Program a certain ring offset voltage and apply it to the Tip/Ring pair via the RSLIC; • Set the RSLIC to Normal Active mode (for MPI interface, LREG6: SCAN_EN = 1, SM[2:0] = 000; for GCI interface, downstream C/I channel: SCAN_EN = 1, SM[2:0] = 000). Set the CODEC to Ring Pause mode (for both MPI and GCI interfaces, LREG6: RING = 1, RING_EN = 0) ...
Page 47
... T RING,DELAY Int. Period Figure - 26 Capacitance Measurement 2. Set the RSLIC operating mode to Internal Ring (for MPI interface, LREG6: SCAN_EN = 1, SM[2:0] = 010; for GCI interface, downstream C/I channel: SCAN_EN = 1, SM[2:0] = 010). 3. Select desired ramp start voltage, end voltage and slope (LREG5 constant parameters for the ramp are selected; ...
Page 48
... RSLIC & CODEC CHIPSET 4. Enable the ramp generator (LREG8: RAMP_EN = 1). Once the RAMP_EN bit is set ramp signal will start from the start voltage and increases its voltage following the programmed slope. When the voltage of the ramp signal finally reaches the programmed ...
Page 49
... Offset Register (word DC Offset in the Coe-RAM). 3.9.6.8 In external ringing mode, the sensed ring current signal is fed to an operational amplifier integrated in the RSLIC. The amplifier will output signal to the CODEC through the RTIN pin for ring trip detection. But this Value amplifier may introduce an offset and affect the ring trip detection result ...
Page 50
... RSLIC & CODEC CHIPSET 4 INTERFACE The RSLIC-CODEC chipset provides two different types of digital interfaces to connect the CODEC to the digital network. One is a PCM interface combined with a serial Microprocessor Interface (PCM/MPI), the other is a General Circuit Interface (GCI). The MPI/GCI pin of the CODEC is used to select the interface ...
Page 51
... RSLIC & CODEC CHIPSET 4.1.2 PCM INTERFACE In PCM/MPI mode, the PCM data (A/µ-law compressed code or linear code) is transferred through the PCM interface. The CODEC provides two transmit and two receive PCM highways for all four channels. The PCM interface consists of eight pins as shown below: ...
Page 52
... RSLIC & CODEC CHIPSET 4.1.2.2 Time Slot Assignment The PCM data of each channel can be assigned to any time slot of the PCM highway. The number of the available time slots is determined by the BCLK frequency. If the BCLK frequency is f kHz, the number of the time slots that can be used is the result of f (kHz) divided by 64 kHz. ...
Page 53
... RSLIC & CODEC CHIPSET four GCI time slots (two for voice data and two for C/I and monitor channels), the remaining four GCI time slots can be used by another chip if you were to tie their control busses together. Hence, for an 8- FSC DCL ...
Page 54
... RSLIC & CODEC CHIPSET FSC DCL DD DU TS0-1 for Monitor and C/I TS2-3 for Linear Voice Data Detail Detail Table - 20 Time Slot Selection For Linear GCI CODEC Monitor and Channel Time Slot C/I Channel 1 Time Slot Time Slot Time Slot Time Slot 1 ...
Page 55
... SCAN_EN and B SM[2:0] bits is for Channel B. The SM[2:0] bits are used to configure the operating mode of the respective RSLIC. The SCAN_EN bit in this byte determines whether the corresponding RSLIC will be accessed. Refer to Operating Modes” on page 89 for detailed information. By properly program the downstream C/I channel byte, users can configure the operating mode of every channel as required ...
Page 56
... RSLIC & CODEC CHIPSET 4.2.4 GCI MONITOR TRANSFER PROTOCOL 4.2.4.1 Monitor Channel Operation In GCI mode, upstream processors access the registers and RAM of the chipset via the monitor channel. Using two monitor control bits MR Master Device Monitor Transmitter Monitor Receiver The transmission of the monitor channel is operated on a pseudo- asynchronous basis: − ...
Page 57
... RSLIC & CODEC CHIPSET MR and MXR Idle and RQT MR and RQT 1st Byte and RQT nth Byte ACK and RQT Wait for ACK MR: MR bit received on DD line MX: MX bit calculated and expected on DU line MXR: MX bit sampled on DU line CLS: ...
Page 58
... POTS interface. “5.2 Register/RAM 4.4 As Figure - 49 CODEC. The RSLIC can work in different modes that are determined by the 104. The RSLIC CODEC through the SLIC mode control pins CSn and M1 to M3. Refer to “6 Operational Description” on page 87 58 IDT82V1671/IDT82V1671A, IDT82V1074 Initial MX State ...
Page 59
... RSLIC & CODEC CHIPSET 5 PROGRAMMING 5.1 OVERVIEW Programming the chipset is realized via the serial microprocessor interface (MPI mode) or GCI monitor channel (GCI mode). In MPI mode, the command or data is transferred via the CI/CO pin. In GCI mode, the command or data is transferred via the DD/DU pin. ...
Page 60
... RSLIC & CODEC CHIPSET '00000' now, the CODEC will stop counting down and the addressing operation is finished. The number of the local registers addressed by a local command is b[4:0]+1. Hence 32(d) local registers can be addressed by one local command. To apply a write local command, total b[4:0]+1 bytes of data should follow to ensure proper operation ...
Page 61
... RSLIC & CODEC CHIPSET data is stored in the FSK-RAM that is shared by all four channels. The FSK-RAM consists of 32 words, 16 bits (two bytes) per word. They are addressed by the FSK-RAM commands. The b[4:0] bits in a FSK-RAM command specify a location in the FSK-RAM to be accessed. In both MPI and GCI modes, when addressing a FSK-RAM word, 16 bits will be written to or read out from this word with MSB first ...
Page 62
... RSLIC & CODEC CHIPSET Table - 23 Coefficient RAM Mapping Word 7 Word 6 Word 5 DC Offset Reserved (default value: 0) Reserved Gain for Impedance Reserved Scaling (GIS) (default value: 0) Digital Gain in Transmit Path Coefficient for Frequency Response Correction in Transmit Path (FRX) (GTX) (default: 0 dB) Digital Gain in ...
Page 63
... RSLIC & CODEC CHIPSET 5.3 REGISTERS DESCRIPTION 5.3.1 REGISTERS OVERVIEW Table - 24 Global Registers Mapping Name Function Description b7 GREG1 PLL power down PLL_PD GREG2 Reserved for future use GREG3 PCM configuration L_CODE MCLK selection and GREG4 channel enable Hardware/software reset GREG5 HW_RST ...
Page 64
... RHS slot selection LREG3 Loopback control Reserved LREG4 Coefficient selection FRR LREG5 Coefficient selection V90 CODEC and RSLIC mode LREG6 P_DOWN control Analog Gain Selection, AC/ DC Ring Trip Selection, LREG7 Reserved Ring Generator and Tone Generators Enable Ramp Generator Enable, Level Meter Path Selection ...
Page 65
... RSLIC & CODEC CHIPSET In the following global registers and local registers lists, it should be noted that Read command. R Write command. 2. The reserved bit(s) in the register must be filled in ‘0’ in write operation and will be ignored in read operation. 3. The global or local registers described below are available for both MPI and GCI modes except for those with special statement. ...
Page 66
... RSLIC & CODEC CHIPSET GREG4: Master Clock Selection and Channel Program Enable, Read/Write (23H/A3H) b7 Command R/W I/O data CH_EN[3:0] Channel programming enable. In MPI mode, the channel programming enable command is used to specify the channel(s) to which the subsequent local command or Coe-RAM command will be applied. The CH_EN[3:0] bits enable Channel 4 to Channel 1 for programming, respectively ...
Page 67
... RSLIC & CODEC CHIPSET RCH_SEL[ The local registers of Channel 3 will not be reset after executing a software reset command (default)); RCH_SEL[ The local registers of Channel 3 will be reset after executing a software reset command; RCH_SEL[ The local registers of Channel 2 will not be reset after executing a software reset command (default); ...
Page 68
... RSLIC & CODEC CHIPSET CONF_CS[1:0] = 01: Channel 2 is selected; CONF_CS[1:0] = 10: Channel 3 is selected; CONF_CS[1:0] = 11: Channel 4 is selected. GREG8: Three-Party Conference Gain Setting, Read/Write (27H/A7H) b7 Command R/W I/O data G_CONF[7:0] Gain of three-party conference. The gain is calculated by the following formula: Gain = G_CONF[7:0] / 256 The default value of G_CONG[7:0] bits is 0(d). ...
Page 69
... RSLIC & CODEC CHIPSET GREG12: Receive Time Slot and Highway Selection for Part C in Three-Party Conference, Read/Write (2BH/ABH) b7 Command R/W RHS_C I/O data RHS_C Receive PCM highway selection for part C in three-party conference RHS_C = 0: RHS_C = 1: RT_C[6:0] Receive time slot selection for part C in three-party conference. ...
Page 70
... RSLIC & CODEC CHIPSET GREG16: Level Meter Count_Number High 3 bits; Level Meter On/Off, Channel Selection and Once/Continuous Measurement, Read/Write (2FH/AFH) b7 Command R/W LM_ONCE I/O data LM_EN LM_ONCE Execution mode of the integrator in level meter. The integration can be executed continuously or once after every initia- tion ...
Page 71
... RSLIC & CODEC CHIPSET The default value of 0 means that no data bytes will be sent out. GREG21: FSK Seizure Length Register, Read/Write (34H/B4H) b7 Command R/W I/O data The seizure length is the number of '01' pairs that represent the seizure phase. The seizure length is two times of the value of the FSK_SL[7:0] bits. The value of the FSK_SL[7:0] bits is valid from 0 to 255(d), corre- sponding to the seizure length from 0 to 510 (d) ...
Page 72
... Interrupt polarity selection. The INT_POL bit determines the valid polarity of all the interrupt signals including the INT_CHA and INT_CHB bits in GCI C/I channel. INT_POL = 0: INT_POL = 1: GREG25: Reserved This register is reserved for future use. GREG26: RSLIC Status, Read (39H); Interrupt Clear, Write (B9H) b7 Command R/W GK[3] I/O data In MPI mode, when applying a read operation to this register, the off-hook and ground-key status of all four channels will be read out ...
Page 73
... RSLIC & CODEC CHIPSET 5.3.3 LOCAL REGISTERS LIST LREG1: Transmit Time Slot and Transmit Highway Selection, Read/Write (00H/80H). This register is used for MPI mode only. b7 Command R/W THS I/O data THS Transmit PCM highway selection for the specified channel. THS = 0: THS = 1: TT[6:0] Transmit time slot selection for the specified channel ...
Page 74
... RSLIC & CODEC CHIPSET CUTOFF = 0: CUTOFF = 1: LREG4: Coefficient Selection, Read/Write (03H/83H) b7 Command R/W FRR I/O data This register determines whether the default values or the coefficients in Coe-RAM is selected for the programmable filters, tone genera- tors and DC offset compensation. FRR Coefficient selection for the Frequency Response correction in the Receive path ...
Page 75
... RAMP = 1: The lower four bits in this register are used to control the operating mode of the RSLIC. These four bits are used for MPI mode only. (In GCI mode, the SCAN_EN and SM[2:0] bits in the downstream C/I channel byte control the operating mode of the RSLIC. Refer to “ ...
Page 76
... RSLIC & CODEC CHIPSET SM[2:0] = '011': SM[2:0] = '100': SM[2:0] = '101': SM[2:0] = '110': SM[2:0] = '111': LREG7: Analog Gain Selection, AC/DC Ring Trip Selection, Ring Generator and Tone Generators Enable, Read/Write (06H/86H) b7 Command R/W Reserved I/O data IM_629 Analog Gain for Impedance Scaling (AGIS) ...
Page 77
... RSLIC & CODEC CHIPSET DC_SRC DC transmit/receive path selection for level meter DC_SRC = 0: DC_SRC = 1: UTD_SRC UTD source selection UTD_SRC = 0: UTD_SRC = 1: UTD_EN Enable the universal tone detection unit UTD_EN = 0: UTD_EN = 1: LREG9: Level Meter Source and Shift Factor Selection, Read/Write (08H/88H) b7 Command R/W I/O data K[3:0] Shift factor selection for the level meter ...
Page 78
... RSLIC & CODEC CHIPSET LM_RECT Enable the rectifier in the level meter. LM_RECT = 0: LM_RECT = 1: LM_TH[2:0] Level meter threshold selection. If the absolute value of the level meter result exceeds the selected threshold, the OTHRE bit will be set to 1. LM_TH[2:0] = 000: Threshold is 0.0% (default); LM_TH[2:0] = 001: Threshold is 12.5%; ...
Page 79
... RSLIC & CODEC CHIPSET LREG13: PCM Data High Byte Register, Read Only (0CH) b7 Command 0 I/O data This register is used for the master processor to monitor the transmit ( PCM data. For linear code, the high byte of PCM data is sent to this register before it is transmitted to the PCM Encoder in the transmit path. For compressed code, this register is not used (in this case, when read, a data byte of 00H will be read out) ...
Page 80
... RSLIC & CODEC CHIPSET LREG18: Interrupt Mask Register, Read/Write (11H/91H) b7 Command R/W Reserved I/O data GK_M Mask bit for the ground-key status bits GK[3:0] in GREG26 GK_M = 0: GK_M = 1: HK_M Mask bit for the off-hook status bits HK[3:0] in GREG26 HK_M = 0: HK_M = 1: OTMP_M Mask bit for the over temperature status bit OTMP in LREG21 ...
Page 81
... RSLIC & CODEC CHIPSET LREG20: RSLIC IO Direction Configuration and IO Status Register, Read/Write (13H/93H) b7 Command R/W IO_C[3] I/O data IO_C[2] IO_C[3:0] RSLIC IO direction configuration. The IO_C[3:0] bits determine the directions of the IO4 to IO1 pins, respectively. IO_C[ IO_C[ IO_C[ IO_C[ IO_C[ IO_C[ IO_C[ IO_C[ ...
Page 82
... Level meter result is not ready (default); Level meter result is ready. No special tone signal (e.g., fax/modem) is detected (default); Special tone signal (e.g., fax/modem) is detected Temperature at the RSLIC is below the limit (default); Temperature at the RSLIC is above the limit; Ramp generation is not completed (default); Ramp generation is completed; ...
Page 83
... RSLIC & CODEC CHIPSET 5.4 PROGRAMMING EXAMPLES 5.4.1 PROGRAMMING EXAMPLES FOR MPI MODE 5.4.1.1 Example of Programming the Local Registers via MPI • Writing to LREG2 and LREG1 of Channel 1: 1010,0011 Channel Enable command 0001,0010 Data for GREG4 (Channel 1 is enabled for programming) 1000,0001 Local register write command (The address is '00001', means that data will be written to LREG2 and LREG1 ...
Page 84
... RSLIC & CODEC CHIPSET 5.4.1.2 Example of Programming the Global Registers via MPI Since the global registers are shared by all four channels need to specify the channel(s) before addressing global registers. Except for this, programming global registers are the same as programming local registers. Refer to on page 83 for more information ...
Page 85
... RSLIC & CODEC CHIPSET • Reading from the FSK-RAM: 0100,0001 FSK-RAM read command (The address is '00001', means that word 2 and word 1 will be read.) After this command is executed, data will be sent out as follows: 1000,0001 Identification code byte 1 data read out from high byte of word 2 ...
Page 86
... RSLIC & CODEC CHIPSET byte 2 data read out from low byte of word 8 in block 1 byte 3 data read out from high byte of word 7 in block 1 (the highest two bits (b7b6) are meaningless) byte 4 data read out from low byte of word 7 in block 1 ...
Page 87
... RSLIC 4 M1~M3 6.1.1 The CODEC provides three common mode selection pins and four individual chip selection pins CS1 to CS4 for the four RSLICs to control their operating modes. See The CS1 to CS4 pins of the CODEC are ternary logic pins as illustrated in the following: ...
Page 88
... RSLIC & CODEC CHIPSET FS 7.8125 µs CS1 CS2 CS3 CS4 I/O Control output 125 µs 31.25 µs output output input input input Figure - 39 RSLIC Control Timing Diagram 88 IDT82V1671/IDT82V1671A, IDT82V1074 output input ...
Page 89
... This mode can be used to test the RSLIC-CODEC chipset without external circuits. When the RSLIC is set to internal test mode, it works in a similar way as normal active mode. The only difference is that a built-in resistor will be connected between the TIP and RING pins to form a loop for testing. ...
Page 90
... In this mode, only the AC loop is active, all functions except for the off-hook detection are switched off. The sensed voltage from the RSLIC is fed to an analog comparator in the CODEC via VTAC pin. The loop state can be determined by comparing the sensed voltage with a fixed off-hook threshold ...
Page 91
... IO[3] to IO[0] have their respective mask bits - IO_M[3] to IO_M[0] in LREG19. Each change of the IO[n] bit will generate an interrupt if its mask bit IO_M[n] is set 3). 6.4 INTERRUPT HANDLING The RSLIC-CODEC chipset is capable of generating interrupts for the following event: • Off-hook/on-hook detected • ground-key detected • ground-key polarity changed • ...
Page 92
... RSLIC & CODEC CHIPSET Figure - 42 AC/DC Signal Path and Test Loopbacks 92 IDT82V1671/IDT82V1671A, IDT82V1074 ...
Page 93
... V VBL ≤ If the recommended application circuit Figure - 50 on page 105) is used, the above mentioned RSLIC power on sequence is not necessary. 6.7 CODEC POWER ON SEQUENCE CODEC power on sequence is as follows: 1. Apply Ground to all ground pins; 2. Apply VDD voltage to all power supply pins; ...
Page 94
... RSLIC THERMAL INFORMATION • Parameter Thermal resistance Maximum junction temperature (plastic) 7.1.4 RSLIC POWER CONSUMPTION • Description RSLIC power consumption in power down mode RSLIC power consumption in standby mode RSLIC power consumption in normal active mode Min. Max. −0 VBH − 0.7 VDD + 0 ...
Page 95
... RSLIC & CODEC CHIPSET 7.2 CODEC ELECTRICAL CHARACTERISTICS 7.2.1 CODEC ABSOLUTE MAXIMUM RATINGS • Ratings Supply pins referred to the corresponding ground pin Ground pins referred to any other ground pin Supply pins referred to any other supply pin Analog input and output pins ...
Page 96
... RSLIC & CODEC CHIPSET 7.3 CHIPSET TRANSMISSION CHARACTERISTICS 0 dBm0 of PCM bus is defined as 0.775 Vrms for 600 Ω load. 0 dBm0 of analog input or output of the CODEC is relative to the 0 dBm0 of the PCM bus output or input. Unless otherwise noted, the analog input dBm0, 1020 Hz sine wave. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder ...
Page 97
... RSLIC & CODEC CHIPSET 7.3.5 GROUP DELAY • Parameter Description Transmit delay, relative to 1800 500 Hz to 600 600 Hz to 1000 1000 Hz to 2600 2600 Hz to 2800 Hz Receive delay, relative to 1800 Hz f < 300 300 Hz to 3400 3600 Hz f ≥ 4600 Hz DR Round-trip delay 7 ...
Page 98
... RSLIC & CODEC CHIPSET 7.3.8 INTERCHANNEL CROSSTALK • Parameter Description XT Transmit to receive crosstalk X-R XT Receive to transmit crosstalk R-X XT Transmit to transmit crosstalk X-X XT Receive to receive crosstalk R-R IDT82V1671/IDT82V1671A, IDT82V1074 Min. Typ. Max. Units −85 −78 dB −85 −80 dB −85 −78 dB −85 − Test Conditions 300 Hz to 3400 Hz, 0 dBm0 signal into VTAC of interfering channel ...
Page 99
... RSLIC & CODEC CHIPSET 7.4 CODEC TIMING CHARACTERISTICS 7.4.1 CLOCK TIMING • Symbol Description t1 CCLK period t2 CCLK pulse width t3 CCLK rise and fall time t4 BCLK period t5 BCLK pulse width t6 BCLK rise and fall time t7 MCLK pulse width t8 MCLK rise and fall time ...
Page 100
... RSLIC & CODEC CHIPSET 7.4.2 MICROPROCESSOR INTERFACE TIMING • Symbol Description t12 CS setup time t13 CS pulse width t14 CS off time t15 Input data setup time t16 Input data hold time t17 SLIC output latch valid t18 Output data turn on delay t19 ...
Page 101
... RSLIC & CODEC CHIPSET 7.4.3 PCM INTERFACE TIMING • Symbol Description 1) t22 BCLK period t23 BCLK high time t24 FSC period t25 FSC setup time t26 FSC hold time t27 DR1/DR2 setup time t28 DR1/DR2 hold time t29 DX1/DX2 output delay ...
Page 102
... RSLIC & CODEC CHIPSET • t22 BCLK t25 t26 FSC t27 DR1/DR2 t29 DX1/DX2 t32 TSX1/TSX2 NOTES: 1) The BCLK frequency must be an integer multiple of the FSC frequency. The maximum BCLK frequency is 8.192 MHz. The minimum BCLK frequency is 64 kHz in compressed mode and 128 kHz in linear mode if only one channel is used. The minimum BCLK frequency is 256 kHz in compressed mode and 512 kHz in linear mode if all four channels are used. 2) TSX1 or TSX2 typically delays from the FSC for 8 ∗ ...
Page 103
... RSLIC & CODEC CHIPSET 7.4.4 GCI INTERFACE TIMING • Symbol Description t34 FSC rise and fall time t35 FSC setup time t36 FSC hold time t37 FSC high pulse width t38 DU data delay time t39 DD data delay time t40 DD data hold time • ...
Page 104
... APPLICATION CIRCUITS 8.1 APPLICATION CIRCUIT FOR THE INTERNAL RINGING MODE The RSLIC-CODEC chipset can provide an internal ringing signal without any external components. The amplitude of the internal ringing signal can Vp. The off-hook detection and ring trip detection are also internally performed. ringing mode. ...
Page 105
... RSLIC & CODEC CHIPSET 8.2 APPLICATION CIRCUIT FOR THE EXTERNAL RINGING MODE The chipset also supports the external ringing mode. R PROT PROTECTION Relay R PROT +5V D6 IN4148 D7 IN4148 Ring Generator -48V DC 80Vrms Figure - 50 Application Circuit for the External Ringing Mode Table - 28 External Components in Application Circuits ...
Page 106
... RSLIC & CODEC CHIPSET 9 ORDERING INFORMATION RSLIC (IDT82V1671): IDT XXXXXXX Dev ice Ty pe RSLIC (IDT82V1671A): IDT XXXXXXXX Dev ice Ty pe CODEC (IDT82V1074): XXXXXXX IDT Dev ice Package Process/Temperature Range Blank J 82V1671 X X Package Process/Temperature Range Blank J 82V1671A X X Package Process/Temperature Range ...
Page 107
... RSLIC & CODEC CHIPSET Data Sheet Document History 11/05/2002 pgs. 1, 17, 36 48, 60 85, 88, 94, 103, 104 01/09/2003 pgs. 1, 105 02/28/2003 pgs. 29, 66, 93, 103, 104 04/22/2003 pgs. 73, 93, 94 11/18/2003 pgs. 1, 19, 21, 29, 61, 63, 75 02/16/2004 pgs. 18, 19, 21, 26, 29, 60, 61, 63, 73, 75, 77, 83-85, 93, 94 07/29/2004 pgs ...