XC95144XL-10TQG144I Xilinx Inc, XC95144XL-10TQG144I Datasheet - Page 12

CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP

XC95144XL-10TQG144I

Manufacturer Part Number
XC95144XL-10TQG144I
Description
CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr

Specifications of XC95144XL-10TQG144I

Package
144TQFP
Family Name
XC9500XL
Device System Gates
3200
Maximum Propagation Delay Time
10 ns
Number Of User I/os
117
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
100 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
117
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1375

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Each output driver is designed to provide fast switching with
minimal power noise. All output drivers in the device may be
configured for driving either 3.3V CMOS levels (which are
compatible with 5V TTL levels as well) or 2.5V CMOS levels
by connecting the device output voltage supply (V
3.3V or 2.5V voltage supply.
XC9500XL device can be used in 3.3V only systems and
mixed voltage systems with any combination of 5V, 3.3V
and 2.5V power supplies.
Each output driver can also be configured for slew-rate lim-
ited operation. Output edge rates may be slowed down to
reduce system noise (with an additional time delay of t
under user control. See
The output enable may be generated from one of four
options: a product term signal from the macrocell, any of the
global output enable signals (GTS), always “1,” or always
“0.” There are two global output enables for devices with 72
or fewer macrocells, and four global output enables for
devices with 144 or more macrocells. Any selected output
enable signal may be inverted locally at each pin output to
provide maximal design flexibility.
Each IOB provides user programmable ground pin capabil-
ity. This allows device I/O pins to be configured as additional
ground pins in order to force otherwise unused pins to a low
5V Tolerant I/Os
The I/Os on each XC9500XL device are fully 5V tolerant
even though the core power supply is 3.3 volts. This allows
5V CMOS signals to connect directly to the XC9500XL
inputs without damage. The 3.3V V
must be at least 1.5V before 5V signals are applied to the
I/Os. In mixed 3.3V/2.5V systems, the user pins, the core
power supply (V
(V
DS054 (v2.5) May 22, 2009
Product Specification
CCIO
5V CMOS
5V TTL or
3.3V CMOS or
2.5V CMOS
) may have power applied in any order.
3.3V
2.5V
5V
5V
0V
0V
0V
0V
R
Figure 11: XC9500XL Devices in (a) 3.3V only and (b) Mixed 5V/3.3V/2.5V Systems
CCINT
IN
), and the output power supply
Figure
V
3.3V
CCINT
XC9500XL
CPLD
GND
(a)
12.
Figure 11
V
CCIO
OUT
CCINT
shows how the
3.3V CMOS, 5V TTL
power supply
3.3V
0V
CCIO
SLEW
) to a
www.xilinx.com
)
5V CMOS
5V TTL or
3.3V CMOS or
2.5V CMOS
voltage state, as well as provide for additional device
grounding capability. This grounding of the pin is achieved
by internal logic that forces a logic low output regardless of
the internal macrocell signal, so the internal macrocell logic
is unaffected by the programmable ground pin capability.
Each IOB also provides for bus-hold circuitry (also called a
“keeper”) that is active during valid user operation. The
bus-hold feature eliminates the need to tie unused pins
either high or low by holding the last known state of the input
until the next input signal is present. The bus-hold circuit
drives back the same state via a nominal resistance (R
of 50 kΩ. See
no higher than V
interfacing to 2.5V components.
When the device is not in valid user operation, the bus-hold
circuit defaults to an equivalent 50 kΩ pull-up resistor in
order to provide a known repeatable device state. This
occurs when the device is in the erased state, in program-
ming mode, in JTAG INTEST mode, or during initial
power-up. A pull-down resistor (1 kΩ) may be externally
added to any pin to override the default R
force a low state during power-up or any of these other
modes.
Xilinx proprietary ESD circuitry and high impedance initial
state permit hot plugging cards using these devices.
Pin-Locking Capability
The capability to lock the user defined pin assignments dur-
ing design iteration depends on the ability of the architec-
ture to adapt to unexpected changes. The XC9500XL
devices incorporate architectural features that enhance the
ability to accept design changes while maintaining the same
pinout.
XC9500XL High-Performance CPLD Family Data Sheet
3.3V
2.5V
5V
0V
5V
0V
0V
0V
Figure
IN
CCIO
V
3.3V
CCINT
XC9500XL
13. Note the bus-hold output will drive
to prevent overdriving signals when
CPLD
GND
(b)
V
2.5V
CCIO
OUT
2.5V CMOS
BH
DS054_11_042101
2.5V
resistance to
0V
BH
12
)