XC95144XL-10TQG144I Xilinx Inc, XC95144XL-10TQG144I Datasheet - Page 13

CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP

XC95144XL-10TQG144I

Manufacturer Part Number
XC95144XL-10TQG144I
Description
CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr

Specifications of XC95144XL-10TQG144I

Package
144TQFP
Family Name
XC9500XL
Device System Gates
3200
Maximum Propagation Delay Time
10 ns
Number Of User I/os
117
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
100 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
117
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1375

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
XC95144XL-10TQG144I
Manufacturer:
Xilinx Inc
Quantity:
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Part Number:
XC95144XL-10TQG144I
Manufacturer:
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The XC9500XL architecture provides for superior pin-lock-
ing characteristics with a combination of large number of
routing switches in the FastCONNECT II switch matrix, a
54-wide input Function Block, and flexible, bidirectional
product term allocation within each macrocell. These fea-
tures address design changes that require adding or chang-
ing internal routing, including additional signals into existing
equations, or increasing equation complexity, respectively.
In-System Programming
WARNING: Programming temperature range of
T
One or more XC9500XL devices can be daisy chained
together and programmed in-system via a standard 4-pin
JTAG protocol, as shown in
ming offers quick and efficient design iterations and elimi-
nates package handling. The Xilinx development system
provides the programming data sequence using a Xilinx
DS054 (v2.5) May 22, 2009
Product Specification
A
PIN
= 0° C to +70° C
0
V
CCIO
1.5V
Voltage
Output
Set to PIN
during valid user
operation
0
R
Figure 13: Bus-Hold Logic
Standard
Figure 12: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs
T
SLEW
Drive to
V
Figure
CCIO
(a)
Level
14. In-system program-
Slew-Rate Limited
R
BH
DS054_13_042101
I/O
www.xilinx.com
Time
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
used with a higher density device without the expense of
board rework.
download cable, a third-party JTAG development system,
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence.
All I/Os are 3-stated and pulled high by the bus-hold cir-
cuitry during in-system programming. If a particular signal
must remain low during this time, then a pull-down resistor
may be added to the pin.
External Programming
XC9500XL devices can also be programmed by the Xilinx
HW-130 device programmer as well as third-party program-
mers. This provides the added flexibility of using pre-pro-
grammed devices during manufacturing, with an in-system
programmable option for future enhancements and design
changes.
Reliability and Endurance
All XC9500XL CPLDs provide a minimum endurance level
of 10,000 in-system program/erase cycles and a minimum
data retention of 20 years. Each device meets all functional,
performance, and data retention specifications within this
endurance limit.
IEEE Std 1149.1 Boundary-Scan (JTAG)
XC9500XL devices fully support IEEE Std 1149.1 bound-
ary-scan (JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS,
USERCODE, INTEST, IDCODE, HIGHZ and CLAMP
XC9500XL High-Performance CPLD Family Data Sheet
1.5V
Voltage
Output
0
T
SLEW
Standard
Slew-Rate Limited
(b)
DS054_12_042101
Time
13