XC95144XL-10TQG144I Xilinx Inc, XC95144XL-10TQG144I Datasheet - Page 3

CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP

XC95144XL-10TQG144I

Manufacturer Part Number
XC95144XL-10TQG144I
Description
CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr

Specifications of XC95144XL-10TQG144I

Package
144TQFP
Family Name
XC9500XL
Device System Gates
3200
Maximum Propagation Delay Time
10 ns
Number Of User I/os
117
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
100 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
117
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1375

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Family Overview
The FastFLASH XC9500XL family is a 3.3V CPLD family
targeted for high-performance, low-voltage applications in
leading-edge communications and computing systems,
where high device reliability and low power dissipation is
important. Each XC9500XL device supports in-system pro-
gramming (ISP) and the full IEEE Std 1149.1 (JTAG) bound-
ary-scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL
family is designed to work closely with the Xilinx® Virtex®,
Spartan®-XL and XC4000XL FPGA families, allowing sys-
tem designers to partition logic optimally between fast inter-
face circuitry and high-density general purpose logic. As
shown in
ranges from 800 to 6400 usable gates with 36 to 288 regis-
ters, respectively. Multiple package options and associated
DS054 (v2.5) May 22, 2009
Product Specification
JTAG Port
Table
I/O/GCK
I/O/GSR
I/O/GTS
R
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1, logic density of the XC9500XL devices
Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly.
2 or 4
3
1
3
Controller
Figure 1: XC9500XL Architecture
Blocks
JTAG
I/O
www.xilinx.com
I/O capacity are shown in
members are fully pin-compatible, allowing easy design
migration across multiple density options in a given package
footprint.
The XC9500XL architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system program-
ming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operat-
ing life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 5V, 3.3V, and 2.5V
inputs, and the outputs may be configured for 3.3V or 2.5V
XC9500XL High-Performance CPLD Family Data Sheet
In-System Programming Controller
18
18
18
18
54
54
54
54
Table
2. The XC9500XL family
Macrocells
Macrocells
Macrocells
Macrocells
Function
Function
Function
Function
DS054_01_042001
Block N
Block 1
Block 2
Block 3
1 to 18
1 to 18
1 to 18
1 to 18
3