XC95144XL-10TQG144I Xilinx Inc, XC95144XL-10TQG144I Datasheet - Page 4

CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP

XC95144XL-10TQG144I

Manufacturer Part Number
XC95144XL-10TQG144I
Description
CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr

Specifications of XC95144XL-10TQG144I

Package
144TQFP
Family Name
XC9500XL
Device System Gates
3200
Maximum Propagation Delay Time
10 ns
Number Of User I/os
117
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
100 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
117
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1375

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operation. The XC9500XL device exhibits symmetric full
3.3V output voltage swing to allow balanced rise and fall
times. Additional details can be found in the application
notes listed in
Architecture Description
Each XC9500XL device is a subsystem consisting of multi-
ple Function Blocks (FBs) and I/O Blocks (IOBs) fully inter-
connected by the FastCONNECT II switch matrix. The IOB
provides buffering for device inputs and outputs. Each FB
provides programmable logic capability with extra wide
54inputs and 18 outputs. The FastCONNECT II switch
matrix connects all FB outputs and input signals to the FB
inputs. For each FB, up to 18 outputs (depending on pack-
age pin-count) and associated output enable signals drive
directly to the IOBs. See
Macrocell
Each XC9500XL macrocell may be individually configured
for a combinatorial or registered function. The macrocell
and associated FB logic is shown in
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, clock enable, set/reset, and output enable.
The product term allocator associated with each macrocell
selects how the five direct terms are used.
DS054 (v2.5) May 22, 2009
Product Specification
FastCONNECT II
Switch Matrix
R
"Further Reading" on page
From
Figure
54
1.
Figure
Programmable
AND-Array
17.
Figure 2: XC9500XL Function Block
3.
Allocators
www.xilinx.com
Product
Term
Set/Reset
Function Block
Each Function Block, as shown in
18 independent macrocells, each capable of implementing
a combinatorial or registered function. The FB also receives
global clock, output enable, and set/reset signals. The FB
generates 18 outputs that drive the FastCONNECT switch
matrix. These 18 outputs and their corresponding output
enable signals also drive the IOB.
Logic within the FB is implemented using a sum-of-products
representation. Fifty-four inputs provide 108 true and com-
plement signals into the programmable AND-array to form
90 product terms. Any number of these product terms, up to
the 90 available, can be allocated to each macrocell by the
product term allocator.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
Global
XC9500XL High-Performance CPLD Family Data Sheet
Macrocell 18
1
Macrocell 1
Global
Clocks
3
18
18
18
OUT
To FastCONNECT II
Switch Matrix
PTOE
Figure 2
To I/O Blocks
DS054_02_042101
is comprised of
4