XC95144XL-10TQG144I Xilinx Inc, XC95144XL-10TQG144I Datasheet - Page 5

CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP

XC95144XL-10TQG144I

Manufacturer Part Number
XC95144XL-10TQG144I
Description
CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr

Specifications of XC95144XL-10TQG144I

Package
144TQFP
Family Name
XC9500XL
Device System Gates
3200
Maximum Propagation Delay Time
10 ns
Number Of User I/os
117
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
100 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
117
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1375

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC95144XL-10TQG144I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC95144XL-10TQG144I
Manufacturer:
XILINX
0
Part Number:
XC95144XL-10TQG144I
Manufacturer:
Xilinx Inc.
Quantity:
4 482
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
term clock. Both true and complement polarities of the
selected clock source can be used within each macrocell. A
GSR input is also provided to allow user registers to be set
to a user-defined state.
DS054 (v2.5) May 22, 2009
Product Specification
54
R
Figure
4, the macrocell register clock
Figure 3: XC9500XL Macrocell Within Function Block
Allocator
Product
Term
Additional
Product
Terms
(from other
macrocells)
Additional
Product
Terms
(from other
macrocells)
Product Term Clock Enable
Product Term Clock
Product Term Reset
Product Term Set
Product Term OE
1
0
www.xilinx.com
Set/Reset
Global
XC9500XL High-Performance CPLD Family Data Sheet
Clocks
3
Global
CE
D/T
R
S
Q
OUT
PTOE
To
FastCONNECTII
Switch Matrix
DS054_03_042101
To
I/O Blocks
5