XC3SD3400A-4FGG676I Xilinx Inc, XC3SD3400A-4FGG676I Datasheet - Page 38
XC3SD3400A-4FGG676I
Manufacturer Part Number
XC3SD3400A-4FGG676I
Description
FPGA, SPARTAN-3A, DSP, 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD3400A-4FGG676I
No. Of Logic Blocks
5968
No. Of Gates
3400000
No. Of Macrocells
53712
Family Type
Spartan-3A
No. Of Speed Grades
4
Total Ram Bits
2322432
No. Of I/o's
502
Clock Management
DCM
I/o Supply
RoHS Compliant
Number Of Logic Elements/cells
53712
Number Of Labs/clbs
5968
Number Of I /o
469
Number Of Gates
3400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD3400A-4FGG676I
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC3SD3400A-4FGG676I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC3SD3400A-4FGG676I
Manufacturer:
XILINX
Quantity:
592
Part Number:
XC3SD3400A-4FGG676I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Configurable Logic Block (CLB) Timing
Table 29: CLB (SLICEM) Timing
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
Propagation Times
T
Set/Reset Pulse Width
T
AS
AH
CKO
DICK
CKDI
CH
CL
TOG
ILO
RPW_CLB
The numbers in this table are based on the operating conditions set forth in
Symbol
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
The time it takes for data to travel from the CLB’s
F (G) input to the X (Y) output
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Table
0.63
0.18
1.58
0.00
0.00
0.63
1.33
Min
–
0
–
7.
-5
Max
0.60
0.62
770
Speed Grade
–
–
–
–
–
–
–
0.36
1.88
0.00
0.00
0.75
0.75
1.61
Min
–
0
–
-4
Max
0.68
0.71
667
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
38