PIC16F1507-E/ML Microchip Technology, PIC16F1507-E/ML Datasheet - Page 76

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE

PIC16F1507-E/ML

Manufacturer Part Number
PIC16F1507-E/ML
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507-E/ML

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
QFN-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 8-1:
 2011 Microchip Technology Inc.
Instruction Flow
(INTCON reg.)
Note
Interrupt flag
GIE bit
Instruction
Fetched
Instruction
Executed
CLKOUT
CLKIN
1:
2:
3:
4:
PC
(1)
(2)
External clock. High, Medium, Low mode assumed.
CLKOUT is shown here for timing reference.
T1
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
OSC
Inst(PC - 1)
; See Section 25.0 “Electrical Specifications” .
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Inst(PC + 1)
Sleep
PC + 1
Processor in
Sleep
PC + 2
Preliminary
T1
OSC (3)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
PC + 2
(4)
Forced NOP
PC + 2
PIC16(L)F1507
Forced NOP
Inst(0004h)
0004h
DS41586A-page 76
Inst(0005h)
Inst(0004h)
0005h

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