PIC16F1507-E/P Microchip Technology, PIC16F1507-E/P Datasheet - Page 180

3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE

PIC16F1507-E/P

Manufacturer Part Number
PIC16F1507-E/P
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F1507-E/P

Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
21.2
In Fixed Duty Cycle (FDC) mode, every time the
accumulator overflows, the output is toggled. This
provides a 50% duty cycle, provided that the increment
value remains constant. For more information, see
Figure
The FDC mode is selected by clearing the NxPFM bit
in the NCOxCON register.
21.3
In Pulse Frequency (PF) mode, every time the accumu-
lator overflows, the output becomes active for one or
more clock periods. Once the clock period expires, the
output returns to an inactive state. This provides a
pulsed output.
The output becomes active on the rising clock edge
immediately following the overflow event. For more
information, see
The value of the active and inactive states depends on
the polarity bit, NxPOL in the NCOxCON register.
The PF mode is selected by setting the NxPFM bit in
the NCOxCON register.
21.3.1
When operating in PF mode, the active state of the out-
put can vary in width by multiple clock periods. Various
pulse widths are selected with the NxPWS<2:0> bits in
the NCOxCLK register.
When the selected pulse width is greater than the
accumulator overflow time frame, the output of the
NCOx operation is indeterminate.
21.4
The last stage in the NCOx module is the output polar-
ity. The NxPOL bit in the NCOxCON register selects the
output polarity. Changing the polarity while the inter-
rupts are enabled will cause an interrupt for the result-
ing output transition.
The NCOx output can be used internally by source
code or other peripherals. Accomplish this by reading
the NxOUT (read-only) bit of the NCOxCON register.
 2011 Microchip Technology Inc.
21-2.
FIXED DUTY CYCLE (FDC) MODE
PULSE FREQUENCY (PF) MODE
OUTPUT POLARITY CONTROL
OUTPUT PULSE WIDTH CONTROL
Figure
21-2.
Preliminary
PIC16(L)F1507
DS41586A-page 180

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