PIC16F1507-I/SS Microchip Technology, PIC16F1507-I/SS Datasheet - Page 97

• Manufacturer Part Number: PIC16F1507-I/SS
• Description: 3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SSOP .209in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F1507-I/SS

• Processor Series: PIC16
• Core: PIC16F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 3.5 KB
• Data Ram Size: 128 B
• Interface Type: ICSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 3
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: -
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: -
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

PIC16(L)F1507
REGISTER 10-5:
DS41586A-page 97
bit 7
Legend:
R = Readable bit
S = Bit can only be set
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-1
—
2:
3:
(1)
Unimplemented bit, read as ‘ 1 ’.
The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1 ).
The LWLO bit is ignored during a program memory erase operation (FREE = 1 ).
Unimplemented: Read as ‘ 1 ’
CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
LWLO: Load Write Latches Only bit
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches
FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs an write operation on the next WR command
WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
0 = The program or erase operation completed normally
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
0 = Program/erase operation to the Flash is complete and inactive
RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
0 = Does not initiate a program Flash read
R/W-0/0
CFGS
will be initiated on the next WR command
on any set attempt (write ‘ 1 ’) of the WR bit).
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
(not cleared) in software.
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
LWLO
R/W/HC-0/0
(3)
FREE
Preliminary
(2)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
R/W/HC-x/q
WRERR
R/W-0/0
WREN
 2011 Microchip Technology Inc.
R/S/HC-0/0
WR
R/S/HC-0/0
RD
bit 0