PIC16F726-E/SO Microchip Technology, PIC16F726-E/SO Datasheet

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PIC16F726-E/SO

Manufacturer Part Number
PIC16F726-E/SO
Description
14KB Flash Program, 1.8V-5.5V, 16MHz Internal Oscillator, 8b ADC, CCP, I2C/SPI,
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr

Specifications of PIC16F726-E/SO

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPICE2000 - EMULATOR MPLAB-ICE 2000 POD
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F726-E/SO
Manufacturer:
Microchip Technology
Quantity:
433
PIC16F72X/PIC16LF72X
Data Sheet
28/40/44-Pin Flash Microcontrollers
with nanoWatt XLP Technology
© 2009 Microchip Technology Inc.
DS41341E

Related parts for PIC16F726-E/SO

PIC16F726-E/SO Summary of contents

Page 1

... PIC16F72X/PIC16LF72X 28/40/44-Pin Flash Microcontrollers © 2009 Microchip Technology Inc. with nanoWatt XLP Technology Data Sheet DS41341E ...

Page 2

... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Flash Microcontrollers with nanoWatt XLP Technology Devices Included In This Data Sheet: PIC16F72X Devices: • PIC16F722 • PIC16F726 • PIC16F723 • PIC16F727 • PIC16F724 PIC16LF72X Devices: • PIC16LF722 • PIC16LF726 • PIC16LF723 • PIC16LF727 • PIC16LF724 High-Performance RISC CPU: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • ...

Page 4

... PIC16F72X/PIC16LF72X Program Memory SRAM Device Flash (bytes) (words) PIC16F722/ 2048 128 PIC16LF722 PIC16F723/ 4096 192 PIC16LF723 PIC16F724/ 4096 192 PIC16LF724 PIC16F726/ 8192 368 PIC16LF726 PIC16F727/ 8192 368 PIC16LF727 DS41341E-page 4 8-bit A/D I/Os Interrupts AUSART (ch Yes Yes Yes Yes Yes Timers CCP ...

Page 5

... CCP1/RC2 SCL/SCK/RC3 QFN, UQFN AN2/RA2 V /AN3/RA3 REF T0CKI/CPS6/RA4 CAP (3) (2) V /SS /CPS7/AN4/RA5 V SS CLKIN/OSC1/RA7 CAP (3) V /CLKOUT/OSC2/RA6 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F722/723/726 devices only. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X PIC16F722/723/726/PIC16LF722/723/726 ...

Page 6

... IOC Y — IOC Y ICSPCLK/ICDCLK IOC Y ICSPDAT/ICDDAT — — — — — — — — — — — — — — — — — — — — — — — — (1) — Y MCLR/V PP — — — — © 2009 Microchip Technology Inc. ...

Page 7

... CLKOUT/OSC2/RA6 V / CAP T1CKI/T1OSO/RC0 (1) CCP2 /T1OSI/RC1 CCP1/RC2 SCL/SCK/RC3 CPS8/RD0 CPS9/RD1 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F724/727 devices only. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X RB7/ICSPDAT 40 1 RB6/ICSPCLK 2 39 RB5/AN13/CPS5/T1G 38 3 RB4/AN11/CPS4 4 37 RB3/AN9/CPS3/CCP2 ...

Page 8

... INT/CPS0/AN12/RB0 CPS1/AN10/RB1 CPS2/AN8/RB2 (1) CCP2 /CPS3/AN9/RB3 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F724/727 devices only. DS41341E-page PIC16F724/727 PIC16LF724/727 RC0/T1OSO/T1CKI (3) RA6/OSC2/CLKOUT/V CAP RA7/OSC1/CLKIN RE2/AN7 RE1/AN6 RE0/AN5 (2) (3) RA5/AN4/CPS7/SS /V CAP RA4/CPS6/T0CKI © 2009 Microchip Technology Inc. ...

Page 9

... Pin Diagrams – PIC16F724/727/PIC16LF724/727) 44-PIN QFN ( DT/RX/RC7 CPS12/RD4 CPS13/RD5 CPS14/RD6 CPS15/RD7 INT/CPS0/AN12/RB0 CPS1/AN10/RB1 CPS2/AN8/RB2 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F724/727 devices only. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 1 RA6/OSC2/CLKOUT RA7/OSC1/CLKIN PIC16F724/727 PIC16LF724/727 ...

Page 10

... Y MCLR/V PP — — — — © 2009 Microchip Technology Inc. ...

Page 11

... Appendix A: Data Sheet Revision History......................................................................................................................................... 291 ® Appendix B: Migrating From Other PIC Devices............................................................................................................................. 291 The Microchip Web Site .................................................................................................................................................................... 299 Customer Change Notification Service ............................................................................................................................................. 299 Customer Support ............................................................................................................................................................................. 299 Reader Response ............................................................................................................................................................................. 300 Product Identification System ............................................................................................................................................................ 301 © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X DS41341E-page 11 ...

Page 12

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41341E-page 12 © 2009 Microchip Technology Inc. ...

Page 13

... The PIC16F72X/PIC16LF72X devices are covered by this data sheet. They are available in 28/40/44-pin packages. Figure 1-1 shows a block diagram of the PIC16F722/723/726/PIC16LF722/723/726 and Figure 1-2 shows a block diagram of the PIC16F724/727/PIC16LF724/727 devices. Table 1-1 shows the pinout descriptions. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X devices DS41341E-page 13 ...

Page 14

... RC3 RC4 RC5 RC6 RC7 PORTE RE3 SDI/ SCK/ SDI/ SCK/ SDI/ SCK/ SDO SDO SDO SDA SCL SDA SCL SDA SCL Synchronous Synchronous Synchronous Serial Port Serial Port Serial Port Capacitive Sensing Module CPS6 CPS7 © 2009 Microchip Technology Inc. ...

Page 15

... Timer0 Timer0 V REF Analog-To-Digital Converter AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 CPS0 CPS1 CPS2 CPS3 CPS4 Note 1: PIC16F724/727 only. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Data Bus Data Bus Data Bus 8 Level Stack 8 Level Stack 8 Level Stack RAM (13-bit) ...

Page 16

... CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN — A/D Channel 9 input. AN — Capacitive sensing input 3. ST CMOS Capture/Compare/PWM2 Schmitt Trigger input with CMOS levels I XTAL = Crystal Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels © 2009 Microchip Technology Inc. ...

Page 17

... RD1 CPS9 RD2/CPS10 RD2 CPS10 Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input HV = High Voltage © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ...

Page 18

... Power — Positive supply. Power — Ground reference Schmitt Trigger input with CMOS levels I XTAL = Crystal pins to stabilize the regulator. For more information, see CAP Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels © 2009 Microchip Technology Inc. ...

Page 19

... PIC16F723/LF723 and PIC16F724/LF724 (0000h-0FFFh) and program memory space for the PIC16F726/LF726 and PIC16F727/LF727 (0000h-1FFFh). Accessing a location above the memory boundaries for the PIC16F722/LF722 will cause a wrap-around within the first program memory space. Accessing a location above the memory boundaries for the PIC16F723/LF723 and PIC16F724/LF724 will cause a wrap-around within the first program memory space ...

Page 20

... PIC16F72X/PIC16LF72X FIGURE 2-3: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F726/LF726 AND PIC16F727/LF727 PC<12:0> CALL, RETURN 13 RETFIE, RETLW Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector Page 0 Page 1 On-chip Program Memory Page 2 Page 3 DS41341E-page 20 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs) ...

Page 21

... Register 32 Bytes General Purpose Register 96 Bytes Accesses 70h-7Fh 7Fh Bank 0 Bank 1 Legend: = Unimplemented data memory locations, read as ‘0’ Not a physical register. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X (*) (*) 80h Indirect addr. 100h 81h TMR0 101h 82h PCL 102h 83h STATUS 103h ...

Page 22

... PCLATH 18Ah INTCON 18Bh PMCON1 18Ch Reserved 18Dh Reserved 18Eh Reserved 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h 1EFh Accesses 1F0h 70h-7Fh 1FFh Bank 3 © 2009 Microchip Technology Inc. ...

Page 23

... Bank 0 Bank 1 Legend: = Unimplemented data memory locations, read as ‘0’ Not a physical register Note 1: PORTD, TRISD, ANSELD and ANSELE are not implemented on the PIC16F726/LF726, read as ‘0’ © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X (*) (*) 80h Indirect addr. 100h 81h TMR0 ...

Page 24

... CCP1M1 CCP1M0 136,40 --00 0000 OERR RX9D 155,40 0000 000x 154,40 0000 0000 152,40 0000 0000 137,40 xxxx xxxx 137,40 xxxx xxxx CCP2M1 CCP2M0 136,40 --00 0000 105,41 xxxx xxxx GO/DONE ADON 104,41 --00 0000 © 2009 Microchip Technology Inc. ...

Page 25

... These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’. 4: Accessible only when SSPM<3:0> = 1001. Accessible only when SSPM<3:0> ≠ 1001 This bit is always ‘1’ as RE3 is input only. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE ...

Page 26

... ANSA1 ANSA0 55,41 --11 1111 ANSB1 ANSB0 64,41 --11 1111 — — ANSD1 ANSD0 81,41 1111 1111 ANSE1 ANSE0 86,41 ---- -111 30,40 ---0 0000 INTF RBIF 46,40 0000 000x — RD 190,41 1--- ---0 — — — — — — © 2009 Microchip Technology Inc. ...

Page 27

... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...

Page 28

... Prescaler”. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) OSC WDT Rate 128 256 1 : 128 Refer to Section 12.3 “Timer1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 29

... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) Note 1: Set BOREN<1:0> the Configuration Word register for this bit to control the BOR. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X U-0 U-0 U-0 — ...

Page 30

... PAGESEL SUB_P1 ;Select page 1 CALL : : ORG SUB1_P1 : : RETURN RETLW and RETFIE instruc- CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ;(800h-FFFh) SUB1_P1 ;Call subroutine in ;page 1 (800h-FFFh) 900h ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh) © 2009 Microchip Technology Inc. ...

Page 31

... From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, refer to Figures 2-4 and 2-5. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X EXAMPLE 2-2: MOVLW MOVWF BANKISEL NEXT CLRF INCF BTFSS GOTO CONTINUE 0 IRP ...

Page 32

... PIC16F72X/PIC16LF72X NOTES: DS41341E-page 32 © 2009 Microchip Technology Inc. ...

Page 33

... PWRT 11-bit Ripple Counter WDTOSC Note 1: Refer to the Configuration Word Register 1 (Register 8-1). © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 3-3. ...

Page 34

... If a Status bit is not implemented, that bit will be read as ‘0’. DS41341E-page 34 Condition (2) Program STATUS Counter Register 0000h 0001 1xxx ---- --0x 0000h 000u uuuu ---- --uu 0000h 0001 0uuu ---- --uu 0000h 0000 1uuu ---- -- uuu0 0uuu ---- --uu 0000h 0001 1uuu ---- --u0 ( uuu1 0uuu ---- --uu © 2009 Microchip Technology Inc. PCON Register ...

Page 35

... If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 3.3 Power-up Timer (PWRT) The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset ...

Page 36

... Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP DS41341E-page 36 From TMR0 Clock Source 0 Postscaler Divide by 1 512 PSA 0 To T1G WDTE Cleared until the end of OST © 2009 Microchip Technology Inc. 8 PS<2:0> TO TMR0 1 WDT Reset WDT Cleared ...

Page 37

... Reset V DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X If V falls below V for greater than parameter DD BOR (T ) (see Section 23.0 “Electrical Specifica- BOR tions”), the Brown-out situation will reset the device. ...

Page 38

... PWRT T OSC — T PWRT Condition Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep may have DD Wake-up from Sleep PWRTE = 1 1024 • T 1024 • T OSC OSC — — © 2009 Microchip Technology Inc. ...

Page 39

... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X T PWRT T OST T PWRT T OST DD T PWRT T OST ): CASE 3 DS41341E-page 39 ...

Page 40

... Microchip Technology Inc. ...

Page 41

... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 3-5 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit PIC16F724/727/PIC16LF724/727 only. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X MCLR Reset/ (1) WDT Reset uuuu uuuu --00 0000 1111 1111 ...

Page 42

... POR = unimplemented bit, reads as ‘0’ value depends on condition. Shaded cells are not - STATUS PCON Register Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu Value on Value on Bit 0 all other POR, BOR (1) Resets C 0001 1xxx 000q quuu BOR ---- --qq ---- --uu © 2009 Microchip Technology Inc. ...

Page 43

... IOCB5 IOC-RB6 IOCB6 IOC-RB7 IOCB7 TMR1GIF TMR1GIE © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X The PIC16F72X/PIC16LF72X device family has 12 interrupt sources, differentiated by corresponding interrupt enable and flag bits: • Timer0 Overflow Interrupt • External Edge Detect on INT Pin Interrupt • PORTB Change Interrupt • ...

Page 44

... See Figure 4-2 for timing details (1) (2) Interrupt Latency Inst ( — Inst (PC) Dummy Cycle Dummy Cycle . Synchronous latency = where 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) = instruction cycle time. Latency CY © 2009 Microchip Technology Inc. ...

Page 45

... W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X following the ISR from using invalid data. Examples of key registers include the W, STATUS, FSR and PCLATH registers. Note: The microcontroller does not normally require saving the PCLATH register. However, if computed GOTO’ ...

Page 46

... User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 (1) (2) INTE RBIE T0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-x INTF RBIF bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 47

... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...

Page 48

... Disables the CCP2 interrupt DS41341E-page 48 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. U-0 R/W-0 — CCP2IE bit Bit is unknown ...

Page 49

... No Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software The TMR1 register did not overflow © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...

Page 50

... CCP2IF bit Bit is unknown Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x PS0 1111 1111 1111 1111 TMR1IE 0000 0000 0000 0000 CCP2IE ---- ---0 ---- ---0 TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 © 2009 Microchip Technology Inc. ...

Page 51

... After the cap is fully charged, the device is released from Reset. For more information, refer to Section 23.0 “Electrical Specifications”. See Configuration Word 2 register (Register 8-2) for V enable bits. CAP © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X ). pin is not CAP DS41341E-page 51 ...

Page 52

... PIC16F72X/PIC16LF72X NOTES: DS41341E-page 52 © 2009 Microchip Technology Inc. ...

Page 53

... SSSEL: SS Input Pin Selection bit function is on RA5/AN4/CPS7/SS function is on RA0/AN0/SS/V bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 0 = CCP2 function is on RC1/T1OSI/CCP2 1 = CCP2 function is on RB3/CCP2 © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ...

Page 54

... TRISA3 TRISA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; ;Init PORTA ; ;digital I/O ; ;Set RA<3:2> as inputs ;and set RA<7:4,1:0> ;as outputs R/W-x R/W-x RA1 RA0 bit Bit is unknown R/W-1 R/W-1 TRISA1 TRISA0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 55

... Digital I/O. Pin is assigned to port or Digital special function Analog input. Pin is assigned as analog input Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X R/W-1 R/W-1 R/W-1 ...

Page 56

... Voltage Regulator Capacitor pin (PIC16F72X only) 6.2.2.8 RA7/OSC1/CLKIN Figure 6-6 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a crystal/resonator connection • a clock input © 2009 Microchip Technology Inc. CAP ...

Page 57

... FIGURE 6-1: BLOCK DIAGRAM OF RA0 PIC16F72X only To Voltage Regulator VCAPEN = 00 Data Bus PORTA TRISA RD TRISA ANSA0 RD PORTA To SSP SS Input © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X A/D Converter V DD I/O Pin V SS DS41341E-page 57 ...

Page 58

... RA<3:1> BLOCK DIAGRAM Data Bus PORTA TRISA RD TRISA ANSAx RD PORTA FIGURE 6-3: BLOCK DIAGRAM OF RA4 Data Bus PORTA TRISA RD TRISA ANSA4 RD PORTA To Timer0 Clock MUX To Cap Sensor DS41341E-page I/O Pin A/D Converter V DD I/O Pin V SS © 2009 Microchip Technology Inc. ...

Page 59

... FIGURE 6-4: BLOCK DIAGRAM OF RA5 PIC16F72X only VCAPEN = 01 Data Bus PORTA TRISA RD TRISA ANSA5 RD PORTA To SSP SS Input © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X To Voltage Regulator To A/D Converter To Cap Sensor V DD I/O Pin V SS DS41341E-page 59 ...

Page 60

... Note 1: CLKOUT Enable = 1 When F OSC FIGURE 6-6: BLOCK DIAGRAM OF RA7 Data Bus PORTA TRISA RD TRISA OSC = INTOSC or INTOSCIO RD PORTA DS41341E-page 60 RA7/OSC1 INTOSC (No I/O Selected). RA6/OSC2 Oscillator Circuit V DD I/O Pin V SS Oscillator Circuit V DD I/O Pin V SS © 2009 Microchip Technology Inc. ...

Page 61

... WCOL SSPOV SSPEN TRISA TRISA7 TRISA6 TRISA5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: PIC16F72X only. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE ADCS0 — ...

Page 62

... When a pin change occurs at the same time as a read operation on PORTB, the RBIF flag will always be set. If multiple PORTB pins are configured for the interrupt-on-change, the user may not be able to identify which pin changed state. executing read-modify-write interrupt-on-change feature is © 2009 Microchip Technology Inc. ...

Page 63

... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated PORTB pin configured as an output © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X R/W-x R/W-x R/W-x RB4 RB3 RB2 U = Unimplemented bit, read as ‘0’ ...

Page 64

... ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) . Digital Input buffer disabled. R/W-1 R/W-1 WPUB1 WPUB0 bit Bit is unknown R/W-0 R/W-0 IOCB1 IOCB0 bit Bit is unknown R/W-1 R/W-1 ANSB1 ANSB0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 65

... Figure 6-8 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • a capacitive sensing input © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 6.3.4.6 RB5/AN13/CPS5/T1G Figure 6-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • ...

Page 66

... PIC16F72X/PIC16LF72X FIGURE 6-7: BLOCK DIAGRAM OF RB0 Data Bus WPUB RD WPUB PORTB TRISB RD TRISB ANSB0 RD PORTB IOCB RD IOCB Interrupt-on- Change RD PORTB To External Interrupt Logic DS41341E-page 66 RBPU A/D Converter To Cap Sensor V DD Weak V DD I/O Pin V SS © 2009 Microchip Technology Inc. ...

Page 67

... FIGURE 6-8: BLOCK DIAGRAM OF RB4, RB<2:1> Data Bus WPUB RD WPUB PORTB TRISB RD TRISB ANSB<4,2,1> RD PORTB IOCB RD IOCB Interrupt-on- Change © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X RBPU A/D Converter Cap Sensor EN RD PORTB V DD Weak V DD I/O Pin V SS DS41341E-page 67 ...

Page 68

... CK Q PORTB TRISB RD TRISB ANSB<5,3> RD PORTB IOCB RD IOCB Interrupt-on- Change (1) To CCP2 Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register. DS41341E-page 68 CCP2OUT Enable RBPU CCP2OUT PORTB To A/D Converter To Cap Sensor V DD Weak V DD I/O Pin V SS © 2009 Microchip Technology Inc. ...

Page 69

... FIGURE 6-10: BLOCK DIAGRAM OF RB5 Data Bus WPUB RD WPUB PORTB TRISB RD TRISB ANSB<5,3> RD PORTB IOCB RD IOCB Interrupt-on- Change To Timer1 Gate © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X CCP2OUT Enable RBPU CCP2OUT PORTB To A/D Converter To Cap Sensor V DD Weak V DD I/O Pin V SS DS41341E-page 69 ...

Page 70

... PIC16F72X/PIC16LF72X FIGURE 6-11: BLOCK DIAGRAM OF RB6 ICSP™ MODE DEBUG Data Bus WPUB RD WPUB PORTB TRISB RD TRISB RD PORTB IOCB RD IOCB Interrupt-on- Change ICSPCLK DS41341E-page 70 RBPU PORT_ICDCLK TRIS_ICDCLK PORTB V DD Weak V DD I/O Pin V SS © 2009 Microchip Technology Inc. ...

Page 71

... FIGURE 6-12: BLOCK DIAGRAM OF RB7 ICSP™ MODE DEBUG Data Bus WPUB RD WPUB PORTB TRISB RD TRISB RD PORTB IOCB RD IOCB Interrupt-on- Change ICSPDAT_IN © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X RBPU PORT_ICDDAT TRIS_ICDDAT PORTB V DD Weak V DD I/O Pin V SS DS41341E-page 71 ...

Page 72

... RBIF 0000 000x 0000 000X IOCB0 0000 0000 0000 0000 PS0 1111 1111 1111 1111 RB0 xxxx xxxx xxxx xxxx T1GSS0 0000 0x00 uuuu uxuu TRISB0 1111 1111 1111 1111 WPUB0 1111 1111 1111 1111 © 2009 Microchip Technology Inc. ...

Page 73

... TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated PORTC pin configured as an output © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X The TRISC register (Register 6-11) controls the PORTC pin output drivers, even when they are being used as analog inputs ...

Page 74

... I/O DS41341E-page 74 6.4.8 RC7/RX/DT Figure 6-20 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an asynchronous serial input • a synchronous serial data I/O © 2009 Microchip Technology Inc. ...

Page 75

... Data Bus CCP2OUT PORTC TRISC RD TRISC T1OSCEN RD PORTC (1) To CCP2 Input Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Oscillator RC1/T1OSI RC0/T1OSO 1 0 Circuit V DD I/O Pin V SS Oscillator Circuit V DD I/O Pin V SS DS41341E-page 75 ...

Page 76

... PORTC SSPEN 2 ™ SSPM = I C MODE 2 ™ To SSP I C SCL Input 2 ™ Note Schmitt Trigger has special input levels. 2 ™ Slew Rate limiting controlled by SMP bit of SSPSTAT register. DS41341E-page SSPEN I/O Pin I/O Pin (1) ™ © 2009 Microchip Technology Inc. ...

Page 77

... I C Slew Rate limiting controlled by SMP bit of SSPSTAT register. FIGURE 6-18: BLOCK DIAGRAM OF RC5 SSPEN SSPM = SPI MODE Data Bus SDO PORTC D Q SDO TRISC RD TRISC RD PORTC © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X I/O Pin (1) ™ I/O Pin V SS DS41341E-page 77 ...

Page 78

... SPEN TXEN 0 CSRC 1 SYNC To USART Sync Clock Input FIGURE 6-20: BLOCK DIAGRAM OF RC7 SPEN SYNC Data Bus USART_DT PORTC TRISC RD TRISC RD PORTC SPEN SYNC TXEN SREN CREN To USART Data Input DS41341E-page I/O Pin I/O Pin V SS © 2009 Microchip Technology Inc. ...

Page 79

... T1CKPS1 T1CKPS0 T1OSCEN TXSTA CSRC TX9 TXEN TRISC TRISC7 TRISC6 TRISC5 Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by Port B. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Bit 4 Bit 3 Bit 2 — — — — DC1B0 CCP1M3 CCP1M2 ...

Page 80

... R/W-x R/W-x R/W-x RD4 RD3 RD2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared INITIALIZING PORTD ; ;Init PORTD ;Make PORTD digital ; ;Set RD<3:2> as inputs ;and set RD<7:4,1:0> ;as outputs R/W-x R/W-x RD1 RD0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 81

... Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: ANSELD register is not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as ‘0’. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X (1) R/W-1 R/W-1 R/W-1 ...

Page 82

... I/O • a capacitive sensing input 6.5.9 RD7/CPS15 Figure 6-21 shows the diagram for these pins. They are configurable to function as one of the following: • a general purpose I/O • a capacitive sensing input V DD I/O Pin Cap Sensor © 2009 Microchip Technology Inc. ...

Page 83

... TRISD7 TRISD6 TRISD5 TRISD4 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are not implemented on the PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Bit 4 Bit 3 Bit 2 Bit 1 ...

Page 84

... EXAMPLE 6-5: INITIALIZING PORTE BANKSEL PORTE ; CLRF PORTE ;Init PORTE BANKSEL ANSELE ; CLRF ANSELE ;digital I/O BANKSEL TRISE ; MOVLW B‘00001100’ ;Set RE<2> input MOVWF TRISE ;and set RE<1:0> ;as outputs DS41341E-page 84 are not © 2009 Microchip Technology Inc. ...

Page 85

... This bit is always ‘1’ as RE3 is an input only bit 2-0 TRISE<2:0>: RE<2:0> Tri-State Control bits 1 = PORTE pin configured as an input (tri-stated PORTE pin configured as an output Note 1: TRISE<2:0> are not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as ‘0’. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X U-0 R-x R/W-x (1) RE3 RE2 — ...

Page 86

... RE3 RE2 RE1 (2) (1) (1) — TRISE3 TRISE2 TRISE1 R/W-1 R/W-1 (2) (2) (2) ANSE1 ANSE0 bit Bit is unknown Value on Value on Bit 0 all other POR, BOR Resets ADON --00 0000 --00 0000 ANSE0 ---- -111 ---- -111 RE0 ---- xxxx ---- xxxx (1) TRISE0 ---- 1111 ---- 1111 © 2009 Microchip Technology Inc. ...

Page 87

... RE3/MCLR/V PP Figure 6-23 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up • a programming voltage reference input © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X DS41341E-page 87 ...

Page 88

... BLOCK DIAGRAM OF RE3 ICSP™ Mode Detect In-Circuit Serial Programming™ mode MCLR Circuit MCLR Pulse Filter Data Bus RD TRISE PORTE DS41341E-page I/O Pin A/D Converter V DD Weak High-Voltage Detect I/O Pin V SS Power for Programming Flash © 2009 Microchip Technology Inc. ...

Page 89

... OSC1 Internal Oscillator 500 kHz 0 32x 1 PLL PLLEN (Configuration Word 1) © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of eight modes of operation – External Resistor-Capacitor (RC) with F /4 output on OSC2/CLKOUT ...

Page 90

... IRCF bits takes effect. This is because the old and new frequencies are derived from INTOSC via the postscaler and multiplexer. Start-up delay specifications are located in the Table 23-2 in Specifications”. for more and Section 23.0 “Electrical © 2009 Microchip Technology Inc. ...

Page 91

... ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable MHz/500 kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy MHz/500 kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy bit 1-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X clock. The R/W-0 ...

Page 92

... Code execution continues during this shift. There is no indication that the shift has occurred. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 93

... LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes ...

Page 94

... Alternate pin functions are described in Section 6.1 “Alternate Pin Function”. Output depends upon RC or RCIO clock mode. ) and capacitor (C ) values EXT EXT Value on Value on Bit 0 all other POR, BOR (1) Resets FOSC0 — — — --10 qq-- --10 qq-- TUN0 --00 0000 --uu uuuu © 2009 Microchip Technology Inc. ...

Page 95

... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. ® 4: MPLAB IDE masks unimplemented Configuration bits to ‘0’. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 8.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. ...

Page 96

... U-1 VCAPEN0 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared pin functions are disabled. CAP (1) (1) (1) U-1 U-1 U-1 — — — bit 8 (1) (1) (1) U-1 U-1 U-1 — — — bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 97

... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are reported when using MPLAB IDE. “PIC16F72X/PIC16LF72X Memory Specification” (DS41332) for more information. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X not been Specification” See the Programming DS41341E-page 97 ...

Page 98

... PIC16F72X/PIC16LF72X NOTES: DS41341E-page 98 © 2009 Microchip Technology Inc. ...

Page 99

... V REF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 Reserved FV REF CHS<3:0> © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X (ADC) allows AV DD ADREF = 0x ADREF = 11 ADREF = 10 + 0000 0001 0010 0011 0100 0101 0110 0111 ADC 1000 GO/DONE ...

Page 100

... Table 9-1 gives examples of appro- priate ADC clock selections. Note: Unless using the F system clock frequency will change the ADC adversely affect the ADC result external periods AD specifica any changes in the RC clock frequency, which may © 2009 Microchip Technology Inc. ...

Page 101

... Sleep. FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION T Tcy Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz 8 MHz (2) (2) 100 ns 125 ns 250 ns (2) (2) ...

Page 102

... Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing the user’s responsibility to ensure that the ADC timing requirements are met. Refer to Section 15.0 “Capture/Compare/PWM (CCP) Module” for more information. © 2009 Microchip Technology Inc. RC ...

Page 103

... Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 9.3 “A/D Acquisition Requirements”. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X EXAMPLE 9-1: ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ...

Page 104

... ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current DS41341E-page 104 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) REF R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 105

... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits 8-bit conversion result. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 106

... SS S Ω Ω 10k ln(0.001957 0. 50°C- 25°C /°C ΜS ) has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED © 2009 Microchip Technology Inc. ...

Page 107

... Threshold Voltage T Note 1: Refer to Section 23.0 “Electrical Specifications” FIGURE 9-4: ADC TRANSFER FUNCTION FFh FEh FDh FCh FBh 04h 03h 02h 01h 00h V SS © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X V DD Sampling Switch ≈ 0. ≤ Rss R IC LEAKAGE (1) I ≈ 0. ...

Page 108

... RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TRISA0 1111 1111 1111 1111 TRISB0 1111 1111 1111 1111 TRISE0 ---- 1111 ---- 1111 . Shaded cells are not used for ADC © 2009 Microchip Technology Inc. ...

Page 109

... A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V) Note 1: FVRRDY is always ‘1’ for the PIC16F72X devices. 2: Fixed Voltage Reference output cannot exceed V © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X U-0 U-0 U-0 — ...

Page 110

... PIC16F72X/PIC16LF72X NOTES: DS41341E-page 110 © 2009 Microchip Technology Inc. ...

Page 111

... Oscillator T1GSS = 11 TMR1GE WDTE Low-Power WDT OSC © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...

Page 112

... Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 23.0 “Electrical Specifications”. DS41341E-page 112 © 2009 Microchip Technology Inc. ...

Page 113

... TMR0 Timer0 Module Register TRISA TRISA7 TRISA6 TRISA5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...

Page 114

... PIC16F72X/PIC16LF72X NOTES: DS41341E-page 114 © 2009 Microchip Technology Inc. ...

Page 115

... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X • Selectable Gate Source Polarity • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • ...

Page 116

... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN System Clock ( OSC Instruction Clock (F x OSC Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Oscillator Circuit on T1OSI/T1OSO Pins 1 system clock or they can run Clock Source /4) © 2009 Microchip Technology Inc. ...

Page 117

... Note: When switching from synchronous to asynchronous operation possible to skip an increment. When switching from asynchronous to synchronous operation possible to produce an additional increment. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 12.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...

Page 118

... WDT is enabled, when the CLRWDT instruction is executed, and so on, Toggle mode must be used. A specific sequence is required to put the device into the correct state to capture the next WDT counter interval. © 2009 Microchip Technology Inc. ...

Page 119

... This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X WDT Oscillator WDT Reset Enable Y Y ...

Page 120

... Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 9.2.5 “Special Event Trigger”. © 2009 Microchip Technology Inc. Section 15 utilize OSC ...

Page 121

... FIGURE 12-3: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 12-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X DS41341E-page 121 ...

Page 122

... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF DS41341E-page 122 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL © 2009 Microchip Technology Inc. Cleared by software ...

Page 123

... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Cleared by software DS41341E-page 123 ...

Page 124

... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop DS41341E-page 124 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) OSC /4) OSC ) OSC U-0 R/W-0 — TMR1ON bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 125

... T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 Gate pin 01 = Timer0 Overflow output 10 = TMR2 Match PR2 output 11 = Watchdog Timer scaler overflow Watchdog Timer oscillator is turned on if TMR1GE = 1, regardless of the state of TMR1ON © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X R/W-0 R/W-0 R-x T1GSPM T1GGO/ ...

Page 126

... RB0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TRISB0 1111 1111 1111 1111 TRISC0 1111 1111 1111 1111 TMR1ON 0000 00-0 uuuu uu-u T1GSS0 0000 0x00 uuuu uxuu © 2009 Microchip Technology Inc. ...

Page 127

... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...

Page 128

... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x 0000 0000 0000 0000 TMR1IE TMR1IF 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 © 2009 Microchip Technology Inc. ...

Page 129

... PS<2:0> Note 1: Channels CPS<15:8> are implemented on PIC16F724/727/PIC16LF724/727 only. 2: CPSCH3 is not implemented on PIC16F722/723/726/PIC16LF722/723/726 CPSON = 0, disabling capacitive sensing, no channel is selected. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X sensing module. The capacitive sensing module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: • ...

Page 130

... Refer to Section 12.0 “Timer1 Module with Gate Control” for additional information. TABLE 14-1: TIMER1 ENABLE FUNCTION TMR1ON TMR1GE Timer1 Operation Count Enabled by input 1 1 © 2009 Microchip Technology Inc. Off Off On ...

Page 131

... This frequency should be less than the value obtained during the nominal frequency measurement. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 14.5.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator ...

Page 132

... Timer1, any other source that wakes the part up early will cause the WDT over- flow to be delayed, affecting the value captured by Timer1. 2: Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep. 41341E-page 132 © 2009 Microchip Technology Inc. ...

Page 133

... The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0 Timer0 Clock Source is the capacitive sensing oscillator 0 = Timer0 Clock Source is the T0CKI pin If T0CS = 0 Timer0 clock source is controlled by the core/Timer0 module and is F © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X U-0 R/W-0 R/W-0 — ...

Page 134

... TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1ON 0000 00-0 0000 00-0 T2CKPS0 -000 0000 -000 0000 TRISA0 1111 1111 1111 1111 TRISB0 1111 1111 1111 1111 TRISD0 1111 1111 1111 1111 © 2009 Microchip Technology Inc. ...

Page 135

... If CCP1 is in Capture mode and CCP2 is configured as a Special Event Trigger, CCP2 will clear Timer1, affecting the value captured on the CCP1 pin. Note: CCPRx and CCPx throughout document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X TABLE 15-1: CCP MODE – TIMER RESOURCES REQUIRED CCP Mode Capture Compare PWM ...

Page 136

... Note 1: A/D conversion start feature is available only on CCP2. DS41341E-page 136 R/W-0 R/W-0 R/W-0 DCxB0 CCPxM3 CCPxM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) is started if the ADC module is enabled. CCPx pin is unaffected.) R/W-0 R/W-0 CCPxM1 CCPxM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 137

... Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode or when Timer1 is clocked the capture operation may OSC not work. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 15.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts ...

Page 138

... TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 TMR1ON 0000 00-0 uuuu uu-u T1GSS0 0000 0x00 0000 0x00 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TRISB0 1111 1111 1111 1111 TRISC0 1111 1111 1111 1111 © 2009 Microchip Technology Inc. ...

Page 139

... Note: Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 15.2.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode ...

Page 140

... TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 TMR1ON 0000 00-0 uuuu uu-u T1GSS0 0000 0x00 0000 0x00 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TRISB0 1111 1111 1111 1111 TRISC0 1111 1111 1111 1111 © 2009 Microchip Technology Inc. ...

Page 141

... In PWM mode, CCPRxH is a read-only register. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X The PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). ...

Page 142

... When the 10-bit time base matches the CCPRxH and (refer to 2-bit latch, then the CCPx pin is cleared (refer to Figure 15-3). PULSE WIDTH • CCPRxL:CCPxCON<5:4> • T (TMR2 Prescale Value) OSC = 1/F OSC DUTY CYCLE RATIO ( ) CCPRxL:CCPxCON<5:4> = ---------------------------------------------------------------------- - ( ) 4 PR2 + bits of OSC © 2009 Microchip Technology Inc. ...

Page 143

... PWM frequency. Refer to Section 7.0 “Oscillator Module” for additional details. 15.3.7 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X EQUATION 15-4: PWM RESOLUTION Resolution = Note: ...

Page 144

... CCP2M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 -000 0000 -000 0000 T2CKPS0 0000 0000 0000 0000 TRISB0 1111 1111 1111 1111 1111 1111 TRISC0 1111 1111 © 2009 Microchip Technology Inc. ...

Page 145

... Multiplier x4 SYNC 1 SPBRG BRGH x © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X The AUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length Synchronous • Address detection in 9-bit mode (AUSART) • ...

Page 146

... These registers are detailed in Register 16-1 and Register 16-2, respectively. DS41341E-page 146 MSb Data Stop Recovery F OSC ÷ x16 x64 FERR CREN OERR RSR Register LSb • • • ( START RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE © 2009 Microchip Technology Inc. ...

Page 147

... RCSTA register enables the automatically configures the TX/CK I/O pin as an output. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the AUSART receiver is enabled ...

Page 148

... TX9D data bit. 7. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 bit 0 bit 1 bit 7/8 Word Stop bit Start bit bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. © 2009 Microchip Technology Inc. ...

Page 149

... TRISC7 TRISC6 TRISC5 TXREG AUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF TXIE ...

Page 150

... GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit of the PIR1 register will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. Receiving Data to Section 16.1.2.4 “Receive is cleared. Refer “Receive Overrun Receive Interrupts © 2009 Microchip Technology Inc. to ...

Page 151

... FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 16.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems ...

Page 152

... If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG Start bit Stop bit 7/8 bit © 2009 Microchip Technology Inc. ...

Page 153

... BRG6 BRG5 TRISC TRISC7 TRISC6 TRISC5 TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF TXIE SSPIE CCP1IE ...

Page 154

... Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Synchronous mode. DS41341E-page 154 R/W-0 U-0 R/W-0 (1) SYNC — BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-1 R/W-0 TRMT TX9D bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 155

... RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure TRISx = 1. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X R/W-0 R/W-0 R-0 ...

Page 156

... Baud Rate Formula F /[64 (n+1)] OSC F /[16 (n+1)] OSC F /[4 (n+1)] OSC Value on Value on Bit 0 all other POR, BOR Resets RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 © 2009 Microchip Technology Inc. ...

Page 157

... Microchip Technology Inc. PIC16F72X/PIC16LF72X SYNC = 0, BRGH = 18.432 MHz F = 16.0000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — ...

Page 158

... F = 1.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) — 300 0.16 207 191 1202 0. 2404 0. — — — 21 10417 0. — — — 3 — — — 1 — — — © 2009 Microchip Technology Inc. ...

Page 159

... One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 16.3.1.2 Synchronous Master Transmission Data is transferred out of the device on the RX/DT pin ...

Page 160

... TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 © 2009 Microchip Technology Inc. ...

Page 161

... CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 16.3.1.7 Receiving 9-bit Characters The AUSART supports 9-bit character reception. When ...

Page 162

... POR, BOR Resets RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 000X 0000 000X TRISC0 1111 1111 1111 1111 TX9D 0000 -010 0000 -010 © 2009 Microchip Technology Inc. ...

Page 163

... CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. The first character will immediately transfer to the TSR register and transmit ...

Page 164

... POR, BOR Resets RBIF 0000 000x 0000 000x TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 RX9D 0000 000X 0000 000X TRISC0 1111 1111 1111 1111 TX9D 0000 -010 0000 -010 © 2009 Microchip Technology Inc. ...

Page 165

... Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 0004h will be called. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 16.4.2 SYNCHRONOUS TRANSMIT DURING SLEEP ...

Page 166

... PIC16F72X/PIC16LF72X NOTES: DS41341E-page 166 © 2009 Microchip Technology Inc. ...

Page 167

... Shift Register (SSPSR) LSb MSb General I/O Processor 1 © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X A typical SPI connection between microcontroller devices is shown in Figure 17-1. Addressing of more than one slave device is accomplished via multiple hardware slave select lines. External hardware and additional I/O pins must be used to support multiple slave select addressing ...

Page 168

... SSPBUF Reg SSPSR Reg SDI bit 0 bit 7 Shift Clock SDO SS Control RA5/SS Enable RA0/SS SSSEL 2 Clock Select Edge Select ÷2 Edge Select Prescaler SCK 4 TRISx SSPM<3:0> DS41341E-page 168 Internal Data Bus Write TMR2 Output F OSC 4, 16, 64 © 2009 Microchip Technology Inc. ...

Page 169

... TRIS register as follows: • SDI configured as input • SDO configured as output • SCK configured as output © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 17.1.1.3 Master Mode Setup In Master mode, the data is transmitted/received as soon as the SSPBUF register is loaded with a byte value ...

Page 170

... MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF TXDATA reg = contents of TXDATA MOVWF SSPBUF ;New data to xmit DS41341E-page 170 bit 2 bit 5 bit 4 bit 3 bit 1 bit 5 bit 4 bit 2 bit 1 bit 3 4 Clock Modes bit 0 bit 0 bit 0 bit 0 © 2009 Microchip Technology Inc. ...

Page 171

... the user to determine which data used and what can be discarded. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 17.1.2.2 To enable the serial port, the SSPEN bit of the SSPCON register must be set Slave mode of operation is selected in the SSPM bits of the SSPCON register, the SDI, SDO, SCK pins will be assigned as serial port pins ...

Page 172

... SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41341E-page 172 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 bit 1 bit 0 bit 0 © 2009 Microchip Technology Inc. ...

Page 173

... SSPIF Interrupt Flag SSPSR to SSPBUF © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X When the SPI module resets, the bit counter is cleared to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. Figure 17-6 shows the timing waveform for such a synchronization event ...

Page 174

... When enabled, these pins must be properly configured as input or output. DS41341E-page 174 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4 OSC /16 OSC /64 OSC R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown (1) © 2009 Microchip Technology Inc. ...

Page 175

... UA: Update Address bit 2 Used mode only. bit 0 BF: Buffer Full Status bit 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 176

... TMR1IF 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000 TRISA0 1111 1111 1111 1111 TRISC0 1111 1111 1111 1111 T2CKPS0 -000 0000 -000 0000 © 2009 Microchip Technology Inc. ...

Page 177

... Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect SSPADD Reg Start and Stop bit Detect © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X FIGURE 17-8: Master SDA SCL 2 C The SSP module has six registers for I They are: • SSP Control (SSPCON) register • ...

Page 178

... BF and SSPOV. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. Generate ACK Pulse Yes Yes Stop Condition Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes © 2009 Microchip Technology Inc. ...

Page 179

... For a 10-bit address, the first byte would equal ‘1111 0’, where A9 and A8 are the two MSbs of the address. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X The sequence of events for 10-bit address is as follows for reception: 1 ...

Page 180

... Receiving Address SDA SCL S SSPIF BF SSPOV DS41341E-page 180 Receiving Data ACK ACK Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full. Receiving Data ACK Bus Master sends Stop condition ACK is not sent. © 2009 Microchip Technology Inc. ...

Page 181

... FIGURE 17-11: I C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X DS41341E-page 181 ...

Page 182

... SCL held low while CPU responds to SSPIF Cleared in software SSPBUF is written in software From SSP Interrupt to clear BF flag Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Transmitting Data ACK Service Routine © 2009 Microchip Technology Inc. ...

Page 183

... FIGURE 17-13 SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X DS41341E-page 183 ...

Page 184

... Refer to Application Note AN578, “Use of the SSP Module in the I (DS00578) for more information bus may Note AN554, “Software 2 C™ Bus Master” (DS00554) for more 2 C™ Multi-Master Environment” © 2009 Microchip Technology Inc. ...

Page 185

... CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X 17.2.11 SLEEP OPERATION While in Sleep mode, the I addresses of data, and when an address match or C master device complete byte transfer occurs, wake the processor from Sleep (if SSP interrupt is enabled). ...

Page 186

... When enabled, these pins must be properly configured as input or output using the associated TRIS bit. DS41341E-page 186 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ( MODE) R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown (2) © 2009 Microchip Technology Inc. ...

Page 187

... BF: Buffer Full Status bit Receive Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C Standard Mode (100 kHz and 1 MHz) ...

Page 188

... TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 SSPM0 0000 0000 0000 0000 1111 1111 1111 1111 BF 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 2 C © 2009 Microchip Technology Inc. ...

Page 189

... MOVWF LOWPMBYTE MOVF PMDATH, W MOVWF HIGHPMBYTE © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X The value written to the PMADRH:PMADRL register pair determines which program memory location is read. The read operation will be initiated by setting the RD bit of the PMCON1 register. The program memory flash controller takes two instructions to complete the read, causing the second instruction after the setting the RD bit will be ignored ...

Page 190

... Bit is cleared R/W-x R/W-x R/W-x PMD4 PMD3 PMD2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/S-0 — RD bit Bit is unknown R/W-x R/W-x PMD9 PMD8 bit Bit is unknown R/W-x R/W-x PMD1 PMD0 bit Bit is unknown © 2009 Microchip Technology Inc. ...

Page 191

... Program Memory Read Data Register High Byte PMDATL Program Memory Read Data Register Low Byte Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Program Memory Read. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X R/W-x R/W-x R/W-x PMA12 ...

Page 192

... PIC16F72X/PIC16LF72X NOTES: DS41341E-page 192 © 2009 Microchip Technology Inc. ...

Page 193

... The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X The following peripheral interrupts can wake the device from Sleep: 1. ...

Page 194

... Inst(0005h) Dummy Cycle Inst(0004h) Value on Value on all Bit 0 POR, BOR other Resets IOCB0 0000 0000 0000 0000 RBIF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 CCP2IE ---- ---0 ---- ---0 TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 © 2009 Microchip Technology Inc. ...

Page 195

... GND Data Clock © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X The device is placed into Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/V Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications ...

Page 196

... PIC16F72X/PIC16LF72X NOTES: DS41341E-page 196 © 2009 Microchip Technology Inc. ...

Page 197

... PORTB instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unin- tended consequence of clearing the condition that set the RBIF flag. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X TABLE 21-1: OPCODE FIELD DESCRIPTIONS ...

Page 198

... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2009 Microchip Technology Inc. ...

Page 199

... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. PIC16F72X/PIC16LF72X BCF Syntax: k Operands: Operation: Status Affected: ...

Page 200

... Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. ...

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