PIC16F726-E/SO Microchip Technology, PIC16F726-E/SO Datasheet - Page 164

• Manufacturer Part Number: PIC16F726-E/SO
• Description: 14KB Flash Program, 1.8V-5.5V, 16MHz Internal Oscillator, 8b ADC, CCP, I2C/SPI,
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F726-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F72X/PIC16LF72X
16.3.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 16.3.1.4 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE interrupt enable bit
of the PIE1 register is set, the interrupt generated will
wake the device from Sleep and execute the next
instruction. If the GIE bit is also set, the program will
branch to the interrupt vector.
TABLE 16-9:
DS41341E-page 164
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISC
TXSTA
Legend:
never Idle
Name
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
AUSART Receive Data Register
TMR1GIE
TMR1GIF
TRISC7
AUSART Synchronous Slave
Reception
SPEN
CSRC
Bit 7
GIE
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
TRISC6
ADIE
Bit 6
PEIE
ADIF
RX9
TX9
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
T0IE
TRISC4
CREN
SYNC
Bit 4
INTE
TXIE
TXIF
TRISC3
ADDEN
SSPIE
SSPIF
RBIE
Bit 3
—
CCP1IE
CCP1IF
TRISC2
16.3.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
BRGH
FERR
Bit 2
T0IF
Set the SYNC and SPEN bits and clear the
CSRC bit.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
Set the CREN bit to enable reception.
The RCIF bit of the PIR1 register will be set
when reception is complete. An interrupt will be
generated if the RCIE bit of the PIE1 register
was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register.
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
INTF
Bit 1
Synchronous Slave Reception Set-
up:
TMR1IE
TMR1IF
TRISC0
RX9D
TX9D
RBIF
Bit 0
© 2009 Microchip Technology Inc.
0000 000x
0000 0000
0000 0000
0000 0000
0000 000X
1111 1111
0000 -010
POR, BOR
Value on
0000 000x
0000 0000
0000 0000
0000 0000
0000 000X
1111 1111
0000 -010
Value on
all other
Resets