PIC16LF1518-E/SS Microchip Technology, PIC16LF1518-E/SS Datasheet - Page 131
PIC16LF1518-E/SS
Manufacturer Part Number
PIC16LF1518-E/SS
Description
28-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 1.8V-3.6V 2
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16LF1517-IPT.pdf
(344 pages)
Specifications of PIC16LF1518-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
28KB (16K x 14)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC16LF151x
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 131 of 344
- Download datasheet (3Mb)
REGISTER 12-23: WPUE: WEAK PULL-UP PORTE REGISTER
TABLE 12-7:
TABLE 12-8:
2010 Microchip Technology Inc.
CONFIG1
Legend:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3
bit 2-0
Note 1:
ADCON0
ANSELE
CCPxCON
LATE
PORTE
TRISE
WPUE
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Note 1: These bits are not implemented on the PIC16(L)F1516/8 devices, read as ‘0’.
Name
Name
U-0
—
2:
(1)
— = unimplemented location, read as ‘ 0 ’. Shaded cells are not used by PORTE.
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
PORTE.
13:8
Bits
7:0
Unimplemented: Read as ‘0’
WPUE: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
SUMMARY OF CONFIGURATION WORD WITH PORTE
—
—
—
—
—
—
—
Bit -/7
U-0
CP
—
Bit 6
—
—
—
—
—
—
MCLRE
Bit -/6
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
Bit 5
PWRTE
Bit 13/5
FCMEN
—
—
—
—
—
DCxB<1:0>
CHS<4:0>
U-0
Preliminary
—
Bit 4
—
—
—
—
—
Bit 12/4
IESO
WDTE<1:0>
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
WPUE3
R/W-1/1
WPUE3
Bit 3
RE3
CLKOUTEN
—
—
‘1’
Bit 11/3
PIC16(L)F1516/7/8/9
TRISE2
LATE2
ANSE2
RE2
Bit 2
—
CCPxM<3:0>
Bit 10/2
(1)
U-0
(1)
(1)
—
BOREN<1:0>
GO/DONE
TRISE1
LATE1
ANSE1
RE1
FOSC<2:0>
Bit 1
—
Bit 9/1
(1)
(1)
(1)
U-0
—
TRISE0
LATE0
ANSE0
ADON
RE0
Bit 0
DS41452A-page 131
—
Bit 8/0
—
(1)
(1)
(1)
Register
on Page
U-0
Register
on Page
—
159
130
229
130
129
129
131
46
bit 0
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