PIC16LF1823-I/SL Microchip Technology, PIC16LF1823-I/SL Datasheet - Page 48
PIC16LF1823-I/SL
Manufacturer Part Number
PIC16LF1823-I/SL
Description
3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core, N
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1823-I/SL
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
MI2C, SPI, EUSART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
12
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF1823-I/SL
Manufacturer:
MICROCHIP
Quantity:
44
Part Number:
PIC16LF1823-I/SL
Manufacturer:
MICRO
Quantity:
20 000
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PIC12F/LF1822/PIC16F/LF1823
3.5.2
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-10:
DS41413B-page 48
7
0
0
FSRnH
1
Location Select
LINEAR DATA MEMORY
0
LINEAR DATA MEMORY
MAP
7
FSRnL
0x2000
0x29AF
Bank 30
Bank 0
0x06F
0x020
0x0A0
Bank 1
0x0EF
0x120
Bank 2
0xF20
0xF6F
0x16F
0
Preliminary
3.5.3
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
FIGURE 3-11:
7
1
FSRnH
Location Select
PROGRAM FLASH MEMORY
via
0
the
PROGRAM FLASH
MEMORY MAP
2010 Microchip Technology Inc.
7
FSR/INDF
FSRnL
0x8000
0xFFFF
interface.
Program
Flash
Memory
(low 8
bits)
0x0000
0x7FFF
0
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