PIC16LF1903T-I/MV Microchip Technology, PIC16LF1903T-I/MV Datasheet

7KB Flash, 256B RAM, LCD, 11x10b ADC, NanoWatt XLP 28 UQFN 4x4x0.5mm T/R

PIC16LF1903T-I/MV

Manufacturer Part Number
PIC16LF1903T-I/MV
Description
7KB Flash, 256B RAM, LCD, 11x10b ADC, NanoWatt XLP 28 UQFN 4x4x0.5mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet

Specifications of PIC16LF1903T-I/MV

Processor Series
PIC16LF190x
Core
PIC
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-28
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
-
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
 Details
PIC16LF1902/3
Data Sheet
28-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
LCD Driver and nanoWatt XLP Technology
Preliminary
 2011 Microchip Technology Inc.
DS41455B

Related parts for PIC16LF1903T-I/MV

PIC16LF1903T-I/MV Summary of contents

Page 1

... LCD Driver and nanoWatt XLP Technology  2011 Microchip Technology Inc. PIC16LF1902/3 Data Sheet 28-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary DS41455B ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Two Pins • In-Circuit Debug (ICD) via Two Pins • Enhanced Low-Voltage Programming (LVP) • Programmable Code Protection • Power-Saving Sleep mode  2011 Microchip Technology Inc. PIC16LF1902/3 Extreme Low-Power Management PIC16LF1902/3 with nanoWatt XLP: • Sleep mode 1.8V, typical • Watchdog Timer: 300 nA @ 1.8V, typical • ...

Page 4

... SEG3/RC2 SEG6/RC3 These pins have interrupt-on-change functionality. Note 1: DS41455B-page 4 128 25 11 256 Preliminary LCD (1) 1 (1) 1 (1) RB7 /SEG13/ICSPDAT (1) RB6 /SEG14/ICSPCLK (1) RB5 /AN13/COM1 (1) RB4 /AN11/COM0 (1) RB3 /AN9/SEG26/VLCD3 (1) RB2 /AN8/SEG25/VLCD2 (1) RB1 /AN10/SEG24/VLCD1 (1) RB0 /AN12/INT/SEG0 RC7/SEG8 RC6/SEG9 RC5/SEG10 RC4/T1G/SEG11  2011 Microchip Technology Inc. ...

Page 5

... FIGURE 2: 28-PIN UQFN PACKAGE DIAGRAM FOR PIC16LF1902/3 28-Pin UQFN COM2/AN2/RA2 SEG15/COM3/V +/AN3/RA3 REF SEG4/T0CKI/RA4 SEG5/AN4/RA5 V SS SEG2/CLKIN/RA7 SEG1/CLKOUT/RA6 These pins have interrupt-on-change functionality. Note 1:  2011 Microchip Technology Inc. PIC16LF1902/3 RB3 1 21 RB2 RB1 19 PIC16LF1902/3 4 RB0 RC7/SEG8 7 15 Preliminary (1) /AN9/SEG26/VLCD3 (1) /AN8/SEG25/VLCD2 ...

Page 6

... IOC Y — IOC Y ICSPCLK IOC Y ICSPDAT — — — — — — — — — — — — — — — — — — — — — — — — (1) — Y MCLR/V PP — — — —  2011 Microchip Technology Inc. ...

Page 7

... Development Support............................................................................................................................................................... 217 24.0 Packaging Information.............................................................................................................................................................. 221 Appendix A: Revision History............................................................................................................................................................. 231 Index .................................................................................................................................................................................................. 233 The Microchip Web Site ..................................................................................................................................................................... 237 Customer Change Notification Service .............................................................................................................................................. 237 Customer Support .............................................................................................................................................................................. 237 Reader Response .............................................................................................................................................................................. 238 Product Identification System ............................................................................................................................................................ 239  2011 Microchip Technology Inc. ) ................................................................................................................................ 179 ™ Preliminary PIC16LF1902/3 DS41455B-page 7 ...

Page 8

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS41455B-page 8 to receive the most current information on all of our products. Preliminary  2011 Microchip Technology Inc. ...

Page 9

... Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral ADC Fixed Voltage Reference (FVR) LCD Temperature Indicator Timers Timer0 Timer1  2011 Microchip Technology Inc. PIC16LF1902/3 of the ● ● ● ● ● ● ● ● ● ● ...

Page 10

... CLKOUT Timing Generation CLKIN INTRC Oscillator MCLR See applicable chapters for more information on peripherals. Note 1: DS41455B-page 10 Program Flash Memory CPU Figure 2-1 Timer0 LCD Timer1 Temp. ADC FVR Indicator 10-Bit Preliminary RAM PORTA PORTB PORTC PORTE  2011 Microchip Technology Inc. ...

Page 11

... SEG26 VLCD3 Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal These pins have interrupt-on-change functionality. Note 1:  2011 Microchip Technology Inc. Input Output Type Type TTL CMOS General purpose I/O. AN — A/D Channel 0 input. ...

Page 12

... CMOS General purpose I/O. ST — Master Clear with internal pull-up. HV — Programming voltage. Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels  2011 Microchip Technology Inc. ...

Page 13

... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 20.0 “Instruction Set Summary” details.  2011 Microchip Technology Inc. Saving”, for more details. for more Preliminary PIC16LF1902/3 DS41455B-page 13 ...

Page 14

... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX  2011 Microchip Technology Inc. ...

Page 15

... Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16LF1902 PIC16LF1903  2011 Microchip Technology Inc. 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. implemented for the PIC16LF1902/3 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space ...

Page 16

... Memory 7FFFh Preliminary PROGRAM MEMORY MAP AND STACK FOR PIC16LF1903 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Rollover to Page 0 Rollover to Page 1 7FFFh  2011 Microchip Technology Inc. ...

Page 17

... FSR require one extra instruction cycle to complete. Example 3-2 demonstrates access- ing the program memory via an FSR. The HIGH directive will set bit<7> label points to a location in program memory.  2011 Microchip Technology Inc. PIC16LF1902/3 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ...

Page 18

... Preliminary 3-2. For for detailed Table 3-4. BANKx INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON  2011 Microchip Technology Inc. ...

Page 19

... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2011 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...

Page 20

... Preliminary BANKED MEMORY PARTITIONING Memory Region 00h Core Registers (12 bytes) 0Bh 0Ch Special Function Registers (20 bytes maximum) 1Fh 20h General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh maps for PIC16LF1902 and Table 3-3.  2011 Microchip Technology Inc. ...

Page 21

TABLE 3-3: PIC16LF1902/3 MEMORY MAP BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh ...

Page 22

TABLE 3-3: PIC16LF1902/3 MEMORY MAP (CONTINUED) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 46Fh 4EFh ...

Page 23

... LCDDATA21 — 7B6h — 7B7h 7B8h Unimplemented Read as ‘0’ 7EFh Legend: = Unimplemented data memory locations, read as ‘0’,  2011 Microchip Technology Inc. PIC16LF1902/3 Bank 31 F80h Core Registers (Table 3-2) F8Bh F8Ch Unimplemented Read as ‘0’ FE3h STATUS_SHAD ...

Page 24

... BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 0000 0000 0000  2011 Microchip Technology Inc. ...

Page 25

... Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2:  2011 Microchip Technology Inc. PIC16LF1902/3 Bit 5 Bit 4 Bit 3 Bit 2 — — ...

Page 26

... WR RD 1000 x000 1000 q000 0000 0000 0000 0000 — — — — WPUB1 WPUB0 1111 1111 1111 1111 — — — — — — ---- 1--- ---- 1--- — — — — — —  2011 Microchip Technology Inc. ...

Page 27

... Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2:  2011 Microchip Technology Inc. PIC16LF1902/3 Bit 5 Bit 4 Bit 3 Bit 2 IOCBP5 IOCBP4 ...

Page 28

... Microchip Technology Inc. ...

Page 29

... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556).  2011 Microchip Technology Inc. 3.3.3 COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables ...

Page 30

... Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will 0x05 return the contents of stack address 0x0F. 0x04 0x03 0x02 0x01 0x00 0x1F 0x0000 STKPTR = 0x1F Preliminary through Figure 3-8 for examples Stack Reset Disabled (STVREN = 0) Stack Reset Enabled (STVREN = 1)  2011 Microchip Technology Inc. ...

Page 31

... FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL  2011 Microchip Technology Inc. PIC16LF1902/3 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 ...

Page 32

... Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x10 Preliminary  2011 Microchip Technology Inc. ...

Page 33

... FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note:  2011 Microchip Technology Inc. PIC16LF1902/3 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory ...

Page 34

... FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 DS41455B-page 34 Indirect Addressing 0 7 FSRxH Bank Select 11111 Bank 31 Preliminary 7 FSRxL 0 Location Select  2011 Microchip Technology Inc. ...

Page 35

... FSRnL Location Select 0x2000 0x29AF  2011 Microchip Technology Inc. PIC16LF1902/3 3.5.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF ...

Page 36

... PIC16LF1902/3 NOTES: DS41455B-page 36 Preliminary  2011 Microchip Technology Inc. ...

Page 37

... Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2011 Microchip Technology Inc. PIC16LF1902/3 by device Preliminary DS41455B-page 37 ...

Page 38

... ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin DS41455B-page 38 U-1 R/P-1 R/P-1 — CLKOUTEN BOREN<1:0> R/P-1 R/P-1 U-1 WDTE<1:0> — Unimplemented bit, read as ‘1’ Value when blank or after Bulk Erase Preliminary R/P-1 U-1 — bit 8 R/P-1 R/P-1 FOSC<1:0> bit 0  2011 Microchip Technology Inc. ...

Page 39

... Flash memory (PIC16LF1903 only Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control 00 = 000h to FFFh write-protected, no addresses may be modified by PMCON control  2011 Microchip Technology Inc. PIC16LF1902/3 R/P-1 R/P-1 R/P-1 ...

Page 40

... See Section 10.4 “User ID, Device ID and Configuration for more information on accessing Word Access” these memory locations. For more information on checksum calculation, “PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF 190X Memory Programming (DS41397). DS41455B-page 40 “Write see the Specification” Preliminary  2011 Microchip Technology Inc. ...

Page 41

... Device PIC16LF1902 01 1100 000 PIC16LF1903 01 1100 001 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above).  2011 Microchip Technology Inc DEV<8:3> REV<4:0> Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit DEVICEID< ...

Page 42

... PIC16LF1902/3 NOTES: DS41455B-page 42 Preliminary  2011 Microchip Technology Inc. ...

Page 43

... External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR Enable  2011 Microchip Technology Inc. PIC16LF1902/3 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41455B-page 43 ...

Page 44

... V for a DD BOR , the device BORDC Figure 5-2 for more information. Device Operation upon wake- up from Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD  2011 Microchip Technology Inc. ...

Page 45

... Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive  2011 Microchip Technology Inc. PIC16LF1902/3 (1) T PWRT < T PWRT ...

Page 46

... Upon bringing MCLR high, the device will begin Figure 5-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary Section 9.0 for more information. Table 5-4 Timer configuration. See for more informa- execution immediately (see  2011 Microchip Technology Inc. ...

Page 47

... FIGURE 5-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC  2011 Microchip Technology Inc. PIC16LF1902/3 T PWRT T MCLR T OST Preliminary DS41455B-page 47 ...

Page 48

... ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition PCON Register 00-1 110x uu-u 0uuu uu-u 0uuu uu-0 uuuu uu-u uuuu 00-1 11u0 uu-u uuuu uu-u u0uu 1u-u uuuu u1-u uuuu  2011 Microchip Technology Inc. ...

Page 49

... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2011 Microchip Technology Inc. PIC16LF1902/3 The PCON register bits are shown in R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT ...

Page 50

... Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS41455B-page 50 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — RWDT RMCLR RI — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page — BORRDY 45 POR BOR SWDTEN 77  2011 Microchip Technology Inc. ...

Page 51

... The INTOSC internal oscillator block produces a low and high frequency clock source, LFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these two clock sources.  2011 Microchip Technology Inc. PIC16LF1902/3 Figure 6-1 designated Preliminary DS41455B-page 51 ...

Page 52

... HF-500 kHz 1010/ /32 0111 HF-250 kHz 1001/ /64 0110 HF-125 kHz 1000/ /128 0101 HF-62.5 kHz /256 0100 HF-31.25 kHz 0011 /512 0010 LF-31 kHz 0001 0000 Preliminary Low-Power Mode Event Switch (SCS<1:0>) 2 Primary Clock 00 01 INTOSC 1x  2011 Microchip Technology Inc. ...

Page 53

... Configuration Word 1: • High power, 4-20 MHz (FOSC = 11) • Medium power, 0.5-4 MHz (FOSC = 10) • Low power, 0-0.5 MHz (FOSC = 01)  2011 Microchip Technology Inc. PIC16LF1902/3 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...

Page 54

... HFINTOSC is running and can be utilized. The High-Frequency Internal Oscillator Status Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. Preliminary Section 6.3 (High-Frequency Internal (Low-Frequency Internal HFINTOSC Figure 6-1). The frequency derived  2011 Microchip Technology Inc. ...

Page 55

... Reset) • 250 kHz • 125 kHz • 62.5 kHz • 31.25 kHz • 31 kHz (LFINTOSC)  2011 Microchip Technology Inc. PIC16LF1902/3 Following any Reset, the IRCF<3:0> bits Note: of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz ...

Page 56

... System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <3:0> System Clock DS41455B-page 56 Start-up Time 2-cycle Sync 0 2-cycle Sync  LFINTOSC turns off unless WDT is enabled 2-cycle Sync  0 Preliminary Running Running Running  2011 Microchip Technology Inc. ...

Page 57

... FOSC<1:0> bits in the Configuration Word 1, or from the internal clock source. The OST does not reflect the status of the secondary oscillator.  2011 Microchip Technology Inc. PIC16LF1902/3 6.3.3 SECONDARY OSCILLATOR The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral ...

Page 58

... Secondary oscillator 00 = Clock determined by FOSC<1:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: DS41455B-page 58 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary U-0 R/W-0/0 R/W-0/0 SCS<1:0> — bit 0  2011 Microchip Technology Inc. ...

Page 59

... CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘ 0 ’. Shaded cells are not used by clock sources. Legend:  2011 Microchip Technology Inc. R-0/q U-0 HFIOFR — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional ...

Page 60

... PIC16LF1902/3 NOTES: DS41455B-page 60 Preliminary  2011 Microchip Technology Inc. ...

Page 61

... Many peripherals produce Interrupts. Refer to the cor- responding chapters for details. FIGURE 7-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7>  2011 Microchip Technology Inc. PIC16LF1902/3 A block diagram of the interrupt logic is shown in Figure 7.1 and Figure 7.1. TMR0IF TMR0IE ...

Page 62

... The latency for synchronous interrupts instruction cycles. For asynchronous interrupts, the latency instruction cycles, depending on when the interrupt occurs. See and Figure 7.3 for more details. Preliminary  2011 Microchip Technology Inc. Figure 7-2 ...

Page 63

... Cycle Instruction at PC Interrupt GIE PC-1 PC FSR ADDR PC Execute 3 Cycle Instruction at PC Interrupt GIE PC-1 PC FSR ADDR PC Execute 3 Cycle Instruction at PC  2011 Microchip Technology Inc. Interrupt Sampled during Q1 PC+1 0004h Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 ...

Page 64

... INTF is enabled to be set any time during the Q4-Q1 cycles. DS41455B-page (1) (2) Interrupt Latency Inst ( — Dummy Cycle Dummy Cycle Inst (PC) . Synchronous latency = 3 Section 21.0 “Electrical Preliminary 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) , where T = instruction cycle time Specifications”.  2011 Microchip Technology Inc. ...

Page 65

... ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved.  2011 Microchip Technology Inc. PIC16LF1902/3 Section 8.0 Preliminary DS41455B-page 65 ...

Page 66

... R/W-0/0 R/W-0/0 R/W-0/0 INTE IOCIE TMR0IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary should ensure the R/W-0/0 R-0/0 INTF IOCIF bit 0  2011 Microchip Technology Inc. ...

Page 67

... Unimplemented: Read as ‘0’ bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt  2011 Microchip Technology Inc. PIC16LF1902/3 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. U-0 ...

Page 68

... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. U-0 U-0 R/W-0/0 — — LCDIE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary  2011 Microchip Technology Inc. U-0 U-0 — — bit 0 ...

Page 69

... Unimplemented: Read as ‘0’ bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending  2011 Microchip Technology Inc. PIC16LF1902/3 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...

Page 70

... U-0 U-0 R/W-0/0 — — LCDIF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary  2011 Microchip Technology Inc. should ensure the U-0 U-0 — — bit 0 ...

Page 71

... TMR1GIE ADIE PIE2 — — PIR1 TMR1GIF ADIF PIR2 — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.  2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF PSA — — — ...

Page 72

... PIC16LF1902/3 NOTES: DS41455B-page 72 Preliminary  2011 Microchip Technology Inc. ...

Page 73

... Examples of internal circuitry that might be sourcing current include the FVR module. See 13.0 “Fixed Volt- for more information. age Reference (FVR)”  2011 Microchip Technology Inc. PIC16LF1902/3 8.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...

Page 74

... LCDIF — WDTPS<4:0> Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 66 IOCBF1 IOCBF0 108 IOCBN1 IOCBN0 108 IOCBP1 IOCBP0 108 — TMR1IE 67 — — 68 TMR1IF — 69 — — SWDTEN 77  2011 Microchip Technology Inc. ...

Page 75

... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep  2011 Microchip Technology Inc. PIC16LF1902/3 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41455B-page 75 ...

Page 76

... STATUS register are changed to indicate the event. See Section 3.0 “Memory Organization” WDT STATUS register (Register Mode Active Active Disabled Active Disabled Disabled Preliminary Section 6.0 “Oscillator and 3-1) for more information. WDT Cleared Cleared until the end of OST Unaffected  2011 Microchip Technology Inc. ...

Page 77

... WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1:  2011 Microchip Technology Inc. R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...

Page 78

... Bit 3 Bit 2 IRCF<3:0> — — WDTPS<4:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN PWRTE WDTE<1:0> Preliminary Register Bit 1 Bit 0 on Page SCS<1:0> SWDTEN 77 Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 38 FOSC<2:0>  2011 Microchip Technology Inc. ...

Page 79

... When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register.  2011 Microchip Technology Inc. 10.1.1 PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses ...

Page 80

... Instruction Fetched ignored the next Preliminary FLASH PROGRAM MEMORY READ FLOWCHART Start Read Operation Select (CFGS) Select Word Address (PMADRH:PMADRL) Initiate Read Operation ( NOP execution forced NOP execution forced Data read now in PMDATH:PMDATL End Read Operation  2011 Microchip Technology Inc. ...

Page 81

... Ignored MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2011 Microchip Technology Inc. PIC16LF1902/3 PMADRH,PMADRL PC+3 INSTR ( PMDATH,PMDATL INSTR ( INSTR( INSTR( instruction ignored instruction ignored Forced NOP Forced NOP ...

Page 82

... FIGURE 10-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence Write 055h to PMCON2 Write 0AAh to PMCON2 Initiate Write or Erase Operation ( Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced Unlock Sequence Preliminary  2011 Microchip Technology Inc. End ...

Page 83

... This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 WRITE instruc- tion.  2011 Microchip Technology Inc. PIC16LF1902/3 FIGURE 10-4: FLASH PROGRAM MEMORY ERASE ...

Page 84

... Write AAh ; Set WR bit to begin erase ; NOP instructions are forced as processor starts ; row erase of program memory The processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary  2011 Microchip Technology Inc. ...

Page 85

... Write opera- tions do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF.  2011 Microchip Technology Inc. PIC16LF1902/3 The following steps should be completed to load the write latches and program a row of program memory. ...

Page 86

FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES PMADRH - Row PMADRH<6:0> Address :PMADRL<7:5> Decode ...

Page 87

... Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Write Operation (FREE = 0) Load Write Latches Only (LWLO = 1)  2011 Microchip Technology Inc. PIC16LF1902/3 Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Yes Last word to ...

Page 88

... NOP instructions are forced as processor writes ; all the program memory write latches simultaneously ; to program memory. ; After NOPs, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary  2011 Microchip Technology Inc. ...

Page 89

... Load the starting address of the row to be rewritten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation.  2011 Microchip Technology Inc. PIC16LF1902/3 FIGURE 10-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure x ...

Page 90

... Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS41455B-page 90 10-2, the Function Read Access User IDs Yes Yes Yes Figure 10-2) Figure 10-2) Preliminary Write Access Yes No No  2011 Microchip Technology Inc. ...

Page 91

... RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure x.x) Figure 10-2 PMDAT = No RAM image ? Fail Yes Verify Operation No Last Word ? Yes End Verify Operation  2011 Microchip Technology Inc. PIC16LF1902/3 Preliminary DS41455B-page 91 ...

Page 92

... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 PMADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0  2011 Microchip Technology Inc. ...

Page 93

... Does not initiate a program Flash read. Unimplemented bit, read as ‘ 1 ’. Note 1: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started ( The LWLO bit is ignored during a program memory erase operation (FREE =  2011 Microchip Technology Inc. PIC16LF1902/3 (2) R/W/HC-0/0 R/W/HC-x/q R/W-0/0 FREE ...

Page 94

... CLKOUTEN PWRTE WDTE<1:0> LVP DEBUG LPBOR — — — Preliminary W-0/0 W-0/0 W-0/0 bit 0 Register on Bit 1 Bit 0 Page INTF IOCIF 66 Register Bit 10/2 Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 46 FOSC<2:0> BORV STVREN — 48 — WRT<1:0>  2011 Microchip Technology Inc. ...

Page 95

... Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in  2011 Microchip Technology Inc. PIC16LF1902/3 FIGURE 11-1: Write LATx Write PORTx ...

Page 96

... Preliminary 11-2. Table 11-2. PORTA OUTPUT PRIORITY (1) Function Priority SEG12 (LCD) AN0 RA0 SEG7 AN1 RA1 COM2 AN2 RA2 V + REF COM3 SEG15 AN3 RA3 SEG4 T0CKI RA4 SEG6 AN5 RA5 CLKOUT SEG1 RA6 CLKIN SEG2 RA7  2011 Microchip Technology Inc. ...

Page 97

... Bit is cleared bit 7-4 LATA<7:0>: PORTA Output Latch Value bits Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of Note 1: actual I/O pin values.  2011 Microchip Technology Inc. PIC16LF1902/3 R/W-x/x R-x/x R/W-x/x RA4 RA3 RA2 U = Unimplemented bit, read as ‘ ...

Page 98

... CLKOUTEN PWRTE WDTE<1:0> Preliminary R/W-1/1 R/W-1/1 ANSA1 ANSA0 bit 0 Register Bit 1 Bit 0 on Page ANSA1 ANSA0 98 LATA1 LATA0 97 PS<2:0> 131 RA1 RA0 97 TRISA1 TRISA0 97 Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 38 — FOSC<1:0>  2011 Microchip Technology Inc. ...

Page 99

... Note: mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software.  2011 Microchip Technology Inc. 11.2.2 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The ...

Page 100

... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATB4 LATB3 LATB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RB1 RB0 bit 0 R/W-1/1 R/W-1/1 TRISB1 TRISB0 bit 0 R/W-x/u R/W-x/u LATB1 LATB0 bit 0  2011 Microchip Technology Inc. ...

Page 101

... RB6 TRISB TRISB7 TRISB6 WPUB WPUB7 WPUB6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. Legend:  2011 Microchip Technology Inc. PIC16LF1902/3 R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...

Page 102

... RC7 Priority listed from highest to lowest. Note 1: Preliminary 11-7. Table 11-7. PORTC OUTPUT PRIORITY (1) Function Priority SOSCO (T1OSCO) T1CKI RC0 SOSC1 (T1OSCI) RC1 SEG2 RC2 SEG6 RC3 SEG11 T1G RC4 SEG10 RC5 SEG9 RC6 SEG8 RC7  2011 Microchip Technology Inc. ...

Page 103

... Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is Note 1: return of actual I/O pin values.  2011 Microchip Technology Inc. PIC16LF1902/3 R/W-x/u R/W-x/u R/W-x/u RC4 RC3 RC2 U = Unimplemented bit, read as ‘ ...

Page 104

... Shaded cells are not used by PORTC. Legend: DS41455B-page 104 Bit 5 Bit 4 Bit 3 Bit 2 LATC5 LATC4 LATC3 LATC2 RC5 RC4 RC3 RC2 TRISC5 TRISC4 TRISC3 TRISC2 Preliminary Register Bit 1 Bit 0 on Page LATC1 LATC0 100 RC1 RC0 100 TRISC1 TRISC0 100  2011 Microchip Technology Inc. ...

Page 105

... Unimplemented: Read as ‘0’ bit 3 Unimplemented: Read as ‘1’ bit 2-0 Unimplemented: Read as ‘0’ Unimplemented, read as ‘1’. Note 1:  2011 Microchip Technology Inc. PIC16LF1902/3 11.4.1 PORTE FUNCTIONS AND OUTPUT PRIORITIES No output priorities, RE3 is an input only pin. U-0 R-x/u ...

Page 106

... RE3 — (1) — — — — — — WPUE3 — Preliminary U-0 U-0 U-0 — — — bit 0 Register Bit 1 Bit 0 on Page 121 GO/DONE ADON — — 105 — — 105 — — 106  2011 Microchip Technology Inc. ...

Page 107

... R RBx IOCBPx  2011 Microchip Technology Inc. PIC16LF1902/3 12.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...

Page 108

... R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0  2011 Microchip Technology Inc. ...

Page 109

... IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB7 TRISB6 TRISB Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.  2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 TMR0IE INTE IOCIE TMR0IF ...

Page 110

... PIC16LF1902/3 NOTES: DS41455B-page 110 Preliminary  2011 Microchip Technology Inc. ...

Page 111

... HFINTOSC FOSC<2:0> = 100 and IRCF<3:0> = 000x BOREN<1:0> BOR BOREN<1:0> and BORFS = 1 BOREN<1:0> and BORFS = 1  2011 Microchip Technology Inc. 13.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC is routed through two amplifiers. Each amplifier can be configured to amplify , with 1.024V or the reference voltage 2x, to produce the two possible voltage levels ...

Page 112

... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (Low Range) (High Range Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG — — Preliminary U-0 R/W-0/0 R/W-0/0 — ADFVR<1:0> bit 0 (2) Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 112  2011 Microchip Technology Inc. ...

Page 113

... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.  2011 Microchip Technology Inc. FIGURE 14-1: 14.2 Minimum Operating V Minimum Sensing Temperature ...

Page 114

... PIC16LF1902/3 NOTES: DS41455B-page 114 Preliminary  2011 Microchip Technology Inc. ...

Page 115

... Reserved FVR Buffer1 CHS<4:0> When ADON = 0, all multiplexer inputs are disconnected. Note 1: See ADCON0 register 2:  2011 Microchip Technology Inc. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ADPREF = 00 ...

Page 116

... Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Section 15.2 Preliminary peri- AD Figure 15-2. specifica- AD for Table 15-1 gives examples of appro- , any changes in the RC clock frequency, which may  2011 Microchip Technology Inc. ...

Page 117

... Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit  2011 Microchip Technology Inc DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 16 MHz 8 MHz (2) 125 ns (2) 250 ns (2) (2) 250 ns 500 ns (2) 0.5  s (2) 1.0  ...

Page 118

... ADCON1 register controls the output format. Figure 15-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘ 0 ’ LSB bit 0  2011 Microchip Technology Inc. ...

Page 119

... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.  2011 Microchip Technology Inc. PIC16LF1902/3 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...

Page 120

... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space  2011 Microchip Technology Inc. ...

Page 121

... ADC is disabled and consumes no operating current See Note 1: Section 13.0 “Fixed Voltage Reference (FVR)” See 2: Section 14.0 “Temperature Indicator Module”  2011 Microchip Technology Inc. PIC16LF1902/3 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 122

... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets DD (1) + pin REF + pin as the source of the positive reference, be aware that a REF Section 21.0 “Electrical Specifications” Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 for details.  2011 Microchip Technology Inc. ...

Page 123

... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use.  2011 Microchip Technology Inc. PIC16LF1902/3 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 124

... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0  2011 Microchip Technology Inc. ...

Page 125

... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.  2011 Microchip Technology Inc. source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...

Page 126

... V - REF DS41455B-page 126 V DD Sampling Switch  0.  Rss R IC LEAKAGE (1) I  0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k  ) Analog Input Voltage 1.5 LSB +  2011 Microchip Technology Inc. ...

Page 127

... TRISA6 TRISB TRISB7 TRISB6 FVRCON FVREN FVRRDY x = unknown unchanged, — = unimplemented read as ‘ 0 ’ value depends on condition. Shaded cells are not Legend: used for ADC module.  2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — ...

Page 128

... PIC16LF1902/3 NOTES: DS41455B-page 128 Preliminary  2011 Microchip Technology Inc. ...

Page 129

... OSC 0 T0CKI 1 TMR0SE TMR0CS  2011 Microchip Technology Inc. PIC16LF1902/3 16.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...

Page 130

... Section 21.0 “Electrical Specifications”. 16.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41455B-page 130 Preliminary  2011 Microchip Technology Inc. ...

Page 131

... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information.  2011 Microchip Technology Inc. R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 132

... PIC16LF1902/3 NOTES: DS41455B-page 132 Preliminary  2011 Microchip Technology Inc. ...

Page 133

... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2011 Microchip Technology Inc. • Gate Value Status • Gate Event Interrupt Figure 17 block diagram of the Timer1 module. T1GSPM ...

Page 134

... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN Instruction Clock (F OSC x System Clock (F ) OSC x External Clocking on T1CKI Pin 0 Osc. Circuit on T1OSI/T1OSO Pins 1 LFINTOSC x Preliminary internal clock source is selected, the system clock or they can run Clock Source /4)  2011 Microchip Technology Inc. ...

Page 135

... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.  2011 Microchip Technology Inc. 17.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry ...

Page 136

... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). Preliminary  2011 Microchip Technology Inc. Figure 17-6 for timing ...

Page 137

... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2011 Microchip Technology Inc. PIC16LF1902/3 17.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode ...

Page 138

... PIC16LF1902/3 FIGURE 17-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 17-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41455B-page 138 Preliminary  2011 Microchip Technology Inc ...

Page 139

... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF  2011 Microchip Technology Inc. PIC16LF1902/3 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41455B-page 139 ...

Page 140

... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41455B-page 140 Set by hardware on falling edge of T1GVAL Preliminary  2011 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...

Page 141

... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop  2011 Microchip Technology Inc. PIC16LF1902/3 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ...

Page 142

... Timer1 gate pin 01 = Timer0 overflow output 10 = Reserved 11 = Reserved DS41455B-page 142 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0  2011 Microchip Technology Inc. ...

Page 143

... TRISC7 TRISC6 TMR1CS1 TMR1CS0 T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information.  2011 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF — ...

Page 144

... PIC16LF1902/3 NOTES: DS41455B-page 144 Preliminary  2011 Microchip Technology Inc. ...

Page 145

... Note 1: the LCD module. COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multi- 2: plex displays.  2011 Microchip Technology Inc. 18.1 LCD Registers The module contains the following registers: • LCD Control register (LCDCON) • ...

Page 146

... Once the module is configured, the LCDEN bit of the LCDCON register is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN bit of the LCDCON register. DS41455B-page 146 Data 12 detailed in Preliminary  2011 Microchip Technology Inc. ...

Page 147

... On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 72 segments. Note 1:  2011 Microchip Technology Inc. PIC16LF1902/3 U-0 R/W-0/0 R/W-0/0 CS<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...

Page 148

... DS41455B-page 148 R-0/0 R/W-0/0 R/W-0/0 WA LP<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit Preliminary  2011 Microchip Technology Inc. R/W-1/1 R/W-1/1 bit 0 ...

Page 149

... VLCD1PE: VLCD1 Pin Enable bit 1 = The VLCD1 pin is connected to the internal bias voltage LCDBIAS1 0 = The VLCD1 pin is not connected bit 0 Unimplemented: Read as ‘0’ Normal pin controls of TRISx and ANSELx are unaffected. Note 1:  2011 Microchip Technology Inc. PIC16LF1902/3 U-0 R/W-0/0 R/W-0/0 — VLCD3PE VLCD2PE U = Unimplemented bit, read as ‘ ...

Page 150

... Resistor ladder is at maximum resistance (Minimum contrast). DS41455B-page 150 U-0 U-0 R/W-0/0 — — LCDCST<2:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit Preliminary  2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 bit 0 ...

Page 151

... W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark Pixel off (clear)  2011 Microchip Technology Inc. PIC16LF1902/3 R/W-0/0 R/W-0/0 R/W-0/0 SEn SEn SEn U = Unimplemented bit, read as ‘0’ ...

Page 152

... The prescale values are selectable from 1:1 through 1:16. To Ladder Power Control Static ÷4 4-bit Prog ÷ 32 1/2 ÷2 Prescaler Counter 1/3, 1/4 LP<3:0> LMUX<1:0> Preliminary Segment ÷ Clock Ring Counter  2011 Microchip Technology Inc. ...

Page 153

... LCD LCD FIGURE 18-3: LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM V DD VLCD3PE VLCD3 VLCD2PE VLCD2 VLCD1PE VLCD1  2011 Microchip Technology Inc. TABLE 18-2: LCD Bias 0 ) LCD Bias 1 LCD and LCD Bias 2 LCD LCD Bias 3 , LCD So that the user is not forced to place external compo- ...

Page 154

... Disabling the internal reference ladder results in all of the ladders being disconnected, allowing external voltages to be supplied. Whenever the LCD module is inactive (LCDA = 0), the internal reference ladder will be turned off. Nominal µA 10 µA 100 µA Preliminary  2011 Microchip Technology Inc. ...

Page 155

... Power Mode Power Mode A COM0 SEG0 COM0-SEG0  2011 Microchip Technology Inc. PIC16LF1902/3 The LCDRL register allows switching between two power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the time when the LCD segments transition. ‘B’ Power mode is the remaining time before the segments or commons change again. The LRLAT< ...

Page 156

FIGURE 18-5: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time 32 kHz Clock Ladder Power ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 Control Segment Clock Segment Data ...

Page 157

FIGURE 18-6: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time 32 kHz Clock Ladder Power ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F Control Segment Clock Segment Data Power Mode ...

Page 158

... Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 25 clocks DS41455B-page 158 R/W-0/0 U-0 R/W-0/0 — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets toFigure 18-4): Figure 18-4): Preliminary R/W-0/0 R/W-0/0 LRLAT<2:0> bit 0  2011 Microchip Technology Inc. ...

Page 159

... Power mode ‘B’, the LCD internal FVR buffer is disables. The LCD module automatically turns on the Note: Fixed Voltage Reference when needed.  2011 Microchip Technology Inc. PIC16LF1902/3 The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST = 111. ...

Page 160

... Active 4 61 Active 5 49 Active Preliminary (2) Frame Frequency = (1) /(4 x (LCD Prescaler 1)) (1) /(2 x (LCD Prescaler 2)) (1) /(1 x (LCD Prescaler 3)) (1) /(1 x (LCD Prescaler 4 /256, T1OSC or OSC 18- MHz, TIMER1 @ 1/2 1/3 1/4 122 162 122 81 108  2011 Microchip Technology Inc. ...

Page 161

... SEG10 LCDDATA1, 2 SEG11 LCDDATA1, 3 SEG12 LCDDATA1, 4 SEG13 LCDDATA1, 5 SEG14 LCDDATA1, 6 SEG15 LCDDATA1, 7 SEG24 LCDDATA2, 5 SEG25 LCDDATA2, 6 SEG26 LCDDATA2, 7  2011 Microchip Technology Inc. COM1 COM2 LCDDATAx LCD LCDDATAx Address Segment Address LCDDATA3, 0 LCDDATA6, 0 LCDDATA3, 1 LCDDATA6, 1 LCDDATA3, 2 LCDDATA6, 2 LCDDATA3, 3 LCDDATA6, 3 LCDDATA3, 4 LCDDATA6, 4 ...

Page 162

... Type-A and Type-B waveforms. COM0 pin SEG0 pin SEG1 pin (active) 1 Frame (inactive) Preliminary DC on all the pixels is DC /256, OSC on all pixels is ‘0’ DC Figure 18-18 provide waveforms  2011 Microchip Technology Inc. ...

Page 163

... FIGURE 18-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM0 pin COM1 COM1 pin COM0 SEG0 pin SEG1 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage (inactive) 1 Frame = 2 single segment times. Note:  2011 Microchip Technology Inc. (active) 1 Frame 1 Segment Time Preliminary PIC16LF1902 ...

Page 164

... TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 pin COM0 COM1 pin SEG0 pin SEG1 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage (inactive) 1 Frame = 2 single segment times. Note: DS41455B-page 164 (active) 2 Frames 1 Segment Time Preliminary  2011 Microchip Technology Inc. ...

Page 165

... FIGURE 18-11: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 pin COM0 COM1 pin SEG0 pin SEG1 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage (inactive) 1 Frame = 2 single segment times. Note:  2011 Microchip Technology Inc. (active) 1 Frame 1 Segment Time Preliminary PIC16LF1902 ...

Page 166

... TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 pin COM0 COM1 pin SEG0 pin SEG1 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage (inactive) 1 Frame = 2 single segment times. Note: DS41455B-page 166 (active) 2 Frames 1 Segment Time Preliminary  2011 Microchip Technology Inc. ...

Page 167

... TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note:  2011 Microchip Technology Inc. COM0 pin COM1 pin COM2 pin SEG0 and SEG2 pins SEG1 pin (inactive) (active) 1 Segment Time ...

Page 168

... TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note: DS41455B-page 168 COM0 pin COM1 pin COM2 pin SEG0 pin SEG1 pin (inactive) (active) 1 Segment Time Preliminary Frames  2011 Microchip Technology Inc. ...

Page 169

... TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note:  2011 Microchip Technology Inc. COM0 pin COM1 pin COM2 pin SEG0 and SEG2 pins SEG1 pin (inactive) (active) 1 Segment Time ...

Page 170

... TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note: DS41455B-page 170 COM0 pin COM1 pin COM2 pin SEG0 pin SEG1 pin (inactive) (active) 1 Segment Time Preliminary Frames  2011 Microchip Technology Inc. ...

Page 171

... TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM0 pin COM2 COM1 pin COM1 COM0 COM2 pin COM3 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note:  2011 Microchip Technology Inc. SEG0 pin SEG1 pin (active) (inactive) 1 Frame 1 Segment Time Preliminary PIC16LF1902 ...

Page 172

... TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM0 pin COM2 COM1 pin COM1 COM0 COM2 pin COM3 pin COM0-SEG0 segment voltage COM0-SEG1 segment voltage 1 Frame = 2 single segment times. Note: DS41455B-page 172 SEG0 pin SEG1 pin (active) (inactive) 2 Frames 1 Segment Time Preliminary  2011 Microchip Technology Inc. ...

Page 173

... WERR bit of the LCDCON register is set and the write does not occur. The LCD frame interrupt is not generated Note: when the Type-A waveform is selected and when the Type-B with no multiplex (static) is selected.  2011 Microchip Technology Inc. PIC16LF1902 FINT Preliminary DS41455B-page 173 ...

Page 174

... – FINT FWR ns))  maximum = 1.5 – FWR CY DS41455B-page 174 LCD Interrupt Occurs 2 Frames T FWR Frame Boundary /2 CY /4) – ns) FRAME CY /4) – ns) FRAME CY Preliminary Controller Accesses Next Frame Data FINT Frame Boundary  2011 Microchip Technology Inc. ...

Page 175

... The LCD module current consumption will not decrease in this mode; however, the overall device power consumption will be lower due to the shutdown of the CPU and other peripherals.  2011 Microchip Technology Inc. PIC16LF1902/3 Table 18-8 shows the status of the LCD module during a Sleep while using each of the three available clock sources ...

Page 176

... PIC16LF1902/3 FIGURE 18-20: SLEEP ENTRY/EXIT WHEN SLPEN = 1 COM0 COM1 COM2 SEG0 2 Frames SLEEP Instruction Execution DS41455B-page 176 Wake-up Preliminary  2011 Microchip Technology Inc ...

Page 177

... LCDCON register. 18.13 Disabling the LCD Module To disable the LCD module, write all ‘0’s to the LCDCON register.  2011 Microchip Technology Inc. PIC16LF1902/3 18.14 LCD Current Consumption When using the LCD module the current consumption consists of the following three factors: • ...

Page 178

... COM0 COM0 SEG25 SEG24 151 COM1 COM1 SEG25 SEG24 151 COM2 COM2 SEG25 SEG24 151 COM3 COM3 LP<3:0> 148 VLCD1PE — 149 LRLAT<2:0> 158 151 151 SE<26:24> 151 — — 68 — — 70 — TMR1ON 141  2011 Microchip Technology Inc. ...

Page 179

... NC RJ11-6PIN ® To MPLAB ICD 2 ® The MPLAB ICD 2 produces a V Note: voltage greater than the maximum V specification of the PIC16LF1902/3.  2011 Microchip Technology Inc. Some programmers produce V (9.0V), an external circuit is required to limit the V voltage. See Figure 19-1 to the Specification” IHH ...

Page 180

... Refer to Figure Pin 1 Indicator Pin Description /MCLR ICSPDAT ICSPCLK Connect Preliminary ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT NC 6 ICSPCLK 5 Target PC Board V SS Bottom Side 19-3. Target (ground)  2011 Microchip Technology Inc. ...

Page 181

... See Figure 19-4 information. FIGURE 19-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Signals Data Clock  2011 Microchip Technology Inc. PIC16LF1902/3 for more Normal Connections Isolation devices (as required). * Preliminary Device to be Programmed V DD MCLR/V ...

Page 182

... PIC16LF1902/3 NOTES: DS41455B-page 182 Preliminary  2011 Microchip Technology Inc. ...

Page 183

... MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit.  2011 Microchip Technology Inc. PIC16LF1902/3 20.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation ...

Page 184

... BRA instruction only OPCODE k (literal 9-bit immediate value FSR Offset instructions OPCODE appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 3 OPCODE n = appropriate FSR m = 2-bit mode value OPCODE only 13 OPCODE DS41455B-page 184 (literal (literal (mode) 0 Preliminary  2011 Microchip Technology Inc. ...

Page 185

... Note 1: If the Program Counter (PC) is modified conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP . 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.  2011 Microchip Technology Inc. PIC16LF1902/3 14-Bit Opcode Cycles ...

Page 186

... TO, PD 0110 0100 0000 0000 0110 0010 0000 0001 TO, PD 0110 0011 0110 0fff 0nkk kkkk 0001 0nmm Z 2 0nkk kkkk 2, 3 0001 1nmm 2 1nkk kkkk  2011 Microchip Technology Inc. ...

Page 187

... Description: Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘ 0 ’, the result is placed ‘d’ is ‘ 1 ’, the result is placed in data memory location ‘f’.  2011 Microchip Technology Inc. ANDLW Syntax: Operands: Operation: Status Affected: ...

Page 188

... Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘ 0 ’, the next instruction is executed. If bit ‘b’ is ‘ 1 ’, then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. Preliminary  2011 Microchip Technology Inc. ...

Page 189

... Syntax: [ label ] CLRW Operands: None 00h  (W) Operation: 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set.  2011 Microchip Technology Inc. PIC16LF1902/3 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None 00h  WDT Operation: 0  WDT prescaler, 1   ...

Page 190

... Status Affected: Z Description: Inclusive OR the W register with regis- ter ‘f’. If ‘d’ is ‘ 0 ’, the result is placed in the W register. If ‘d’ is ‘ 1 ’, the result is placed back in register ‘f’. Preliminary  2011 Microchip Technology Inc. INCFSZ f,d IORLW k IORWF f,d ...

Page 191

... Carry flag. A ‘ 0 ’ is shifted into the MSb. If ‘d’ is ‘ 0 ’, the result is placed ‘d’ is ‘ 1 ’, the result is stored back in register ‘f’. 0 register f  2011 Microchip Technology Inc. PIC16LF1902/3 MOVF Move f Syntax: [ label ] 0  ...

Page 192

... Operands: (W)  (f) Operation: Status Affected: None Description: Move data from W register to register ‘f’. Words: 1 Cycles: 1 Example: MOVWF Before Instruction OPTION_REG = 0xFF After Instruction OPTION_REG = 0x4F Preliminary  2011 Microchip Technology Inc. MOVLW k 0x5A W = 0x5A MOVWF f OPTION_REG W = 0x4F W = 0x4F ...

Page 193

... FSRn. FSRn is limited to the range 0000h - FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits.  2011 Microchip Technology Inc. NOP Syntax: Operands: Operation: Status Affected: Description: Words: ...

Page 194

... If ‘d’ is ‘ 0 ’, the result is placed in the W register. If ‘d’ is ‘ 1 ’, the result is stored back in register ‘f’. Words: 1 Cycles: 1 Example: RLF Before Instruction After Instruction Preliminary  2011 Microchip Technology Inc. RETURN RLF f,d C Register f REG1,0 REG1 = 1110 0110 C = ...

Page 195

... The power-down Status bit cleared. Time-out Status bit set. Watchdog Timer and its pres- caler are cleared. The processor is put into Sleep mode with the oscillator stopped.  2011 Microchip Technology Inc. PIC16LF1902/3 SUBLW Subtract W from literal Syntax: [ label ] 0  k  255 Operands (W)  ...

Page 196

... Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘ 0 ’, the result is stored in the W register. If ‘d’ is ‘ 1 ’, the result is stored back in regis- ter ‘f’. Preliminary  2011 Microchip Technology Inc. XORLW k XORWF f,d ...

Page 197

... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2011 Microchip Technology Inc. ........................................................................... -0.  ...

Page 198

... Oscillator mode’s supported frequencies. FIGURE 21-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V 125 -20 -40 1.8 2.0 DS41455B-page 198   T +125° Mode Only 10 16 Frequency (MHz 15% ± 10% + 15% 2.5 3.0 3.5 3.6 V (V) DD Preliminary  2011 Microchip Technology Inc. 20 AND TEMPERATURE ...

Page 199

... SS When NPOR is low, the device is held in Reset. Note 1: 1  s typical POR 2.7  s typical VLOW  2011 Microchip Technology Inc. PIC16LF1902/3 Standard Operating Conditions (unless otherwise stated) -40°C  T Operating temperature -40°C  T Min. Typ† Max. Units 1.8 — ...

Page 200

... F OSC HFINTOSC mode mA 3.0 0 3.6 0.6 1.1 0.8 1.5 mA 1.8 F OSC HFINTOSC mode mA 3.0 0.9 1.6 mA 3.6 1.0 1.7 ; MCLR = V ; WDT disabled Preliminary Conditions Note = 1 MHz = 4 MHz = 500 kHz = 1 MHz = 4 MHz = 8 MHz = 16 MHz  2011 Microchip Technology Inc. ...

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