PIC16LF1904-E/PT Microchip Technology, PIC16LF1904-E/PT Datasheet
PIC16LF1904-E/PT
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PIC16LF1904-E/PT Summary of contents
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... LCD Driver and nanoWatt XLP Technology 2011 Microchip Technology Inc. PIC16LF1904/6/7 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary Data Sheet DS41569A ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Programmable Code Protection • Power-Saving Sleep mode 2011 Microchip Technology Inc. PIC16LF1904/6/7 Extreme Low-Power Management PIC16LF1904/6/7 with nanoWatt XLP: • Sleep mode 1.8V, typical • Watchdog Timer: 300 nA @ 1.8V, typical • Timer1 Oscillator: 500 nA @ 1.8V, typical Analog Features: • Analog-to-Digital Converter (ADC): ...
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... PIC16LF1904/6/7 PIC16LF1904/6/7 Family Types Device PIC16LF1904 4096 256 PIC16LF1906 8192 512 PIC16LF1907 8192 512 COM3 and SEG15 share a pin, so the total segments are limited to 72 for 28 pin devices. Note 1: FIGURE 1: 28-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16LF1906 28-Pin PDIP, SOIC, SSOP ...
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... FIGURE 2: 28-PIN UQFN PACKAGE DIAGRAM FOR PIC16LF1906 28-Pin UQFN COM2/AN2/RA2 SEG15/COM3/V +/AN3/RA3 REF SEG4/T0CKI/RA4 SEG5/AN4/RA5 V SS SEG2/CLKIN/RA7 SEG1/CLKOUT/RA6 2011 Microchip Technology Inc. PIC16LF1904/6/7 RB3/AN9/SEG26/VLCD3 1 21 RB2/AN8/SEG25/VLCD2 RB1/AN10/SEG24/VLCD1 19 PIC16LF1906 4 RB0/AN12/INT/SEG0 RC7/RX/DT/SEG8 7 15 Preliminary DS41569A-page 5 ...
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... PIC16LF1904/6/7 FIGURE 3: 40-PIN PDIP PACKAGE DIAGRAM FOR PIC16LF1904/7 40-Pin PDIP V /MCLR/RE3 PP SEG12/AN0/RA0 SEG7/AN1/RA1 COM2/AN2/RA2 SEG15/V +/AN3/RA3 REF SEG4/T0CKI/RA4 SEG5/AN4/RA5 SEG21/AN5/RE0 SEG22/AN6/RE1 SEG23/AN7/RE2 SEG2/CLKIN/RA7 SEG1/CLKOUT/RA6 T1CKI/T1OSO/RC0 T1OSI/RC1 SEG3/RC2 SEG6/RC3 COM3/RD0 SEG27/RD1 DS41569A-page 6 RB7/ICSPDAT/ICDDAT/SEG13 1 40 RB6/ICSPCLK/ICDCLK/SEG14 39 2 RB5/AN13/COM1 3 38 RB4/AN11/COM0 37 4 RB3/AN9/SEG26/VLCD3 5 36 ...
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... FIGURE 4: 44-PIN TQFP (10X10) PACKAGE DIAGRAM FOR PIC16LF1904/7 44-Pin TQFP (10x10) SEG8/DT/RX/RC7 SEG17/RD4 SEG18/RD5 SEG19/RD6 SEG20/RD7 SEG0/INT/AN12/RB0 VLCD1/SEG24/AN10/RB1 VLCD2/SEG25/AN8/RB2 VLCD3/SEG26/AN9/RB3 2011 Microchip Technology Inc. PIC16LF1904/6 PIC16LF1904 Preliminary NC RC0/T1OSO/T1CKI RA6/CLKOUT/SEG1 RA7/CLKIN/SEG2 RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/SEG5 RA4/T0CKI/SEG4 DS41569A-page 7 ...
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... PIC16LF1904/6/7 FIGURE 5: 40-PIN UQFN (5X5) PACKAGE DIAGRAM FOR PIC16LF1904/7 40-Pin UQFN (5x5) SEG8/DT/RX/RC7 SEG17/RD4 SEG18/RD5 SEG19/RD6 SEG20/RD7 SEG0/INT/AN12/RB0 VLCD1/SEG24/AN10/RB1 VLCD2/SEG25/AN8/RB2 DS41569A-page PIC16LF1904 Preliminary RC0/T1OSO/T1CKI RA6/CLKOUT/SEG1 RA7/CLKIN/SEG2 RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/SEG5 RA4/T0CKI/SEG4 2011 Microchip Technology Inc. ...
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... Note 1: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. 2: 28-pin only pin location (PIC16LF1906). Location different on 40/44-pin device. 3: 40/44-pin only pin location (PIC16LF1904/1907). Location different on 28-pin device. 2011 Microchip Technology Inc. PIC16LF1904/6/7 17 AN0 — ...
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... PIC16LF1904/6/7 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 19 3.0 Memory Organization ................................................................................................................................................................. 21 4.0 Device Configuration .................................................................................................................................................................. 43 5.0 Resets ........................................................................................................................................................................................ 49 6.0 Oscillator Module........................................................................................................................................................................ 57 7.0 Interrupts .................................................................................................................................................................................... 67 8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 79 9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 81 10.0 Flash Program Memory Control ................................................................................................................................................. 85 11.0 I/O Ports ................................................................................................................................................................................... 101 12.0 Interrupt-on-Change ................................................................................................................................................................. 117 13 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Preliminary DS41569A-page 11 ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 12 Preliminary 2011 Microchip Technology Inc. ...
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... DEVICE OVERVIEW The PIC16LF1904/6/7 are described within this data sheet. They are available in 28, 40 and 44-pin pack- ages. Figure 1-1 shows a block diagram of the PIC16LF1904/6/7 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. ...
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... PIC16LF1904/6/7 FIGURE 1-1: PIC16LF1904/6/7 BLOCK DIAGRAM CLKOUT Timing Generation CLKIN INTRC Oscillator MCLR LCD See applicable chapters for more information on peripherals. Note 1: DS41569A-page 14 Program Flash Memory CPU Figure 2-1 Timer0 Timer1 ADC Temp. FVR Indicator 10-Bit Preliminary RAM PORTA PORTB PORTC ...
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... TABLE 1-2: PIC16LF1904/6/7 PINOUT DESCRIPTION Name Function RA0/AN0/SEG12 RA0 AN0 SEG12 RA1/AN1/SEG7 RA1 AN1 SEG7 RA2/AN2/COM2 RA2 AN2 COM2 (2) RA3/AN3/V +/COM3 / RA3 REF SEG15 AN3 V REF COM3 SEG15 RA4/T0CKI/SEG4 RA4 T0CKI SEG4 RA5/AN4/SEG5 RA5 AN4 SEG5 RA6/CLKOUT/SEG1 RA6 CLKOUT SEG1 RA7/CLKIN/SEG2 ...
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... PIC16LF1904/6/7 TABLE 1-2: PIC16LF1904/6/7 PINOUT DESCRIPTION (CONTINUED) Name Function (1) RB3 /AN9/SEG26/VLCD3 RB3 AN9 SEG26 VLCD3 (1) RB4 /AN11/COM0 RB4 AN11 COM0 (1) RB5 /AN13/COM1 RB5 AN13 COM1 (1) RB6 /ICSPCLK/ICDCLK/ RB6 SEG14 ICSPCLK ICDCLK SEG14 (1) RB7 /ICSPDAT/ICDDAT/ RB7 SEG13 ICSPDAT ICDDAT SEG13 RC0/T1OSO/T1CKI RC0 ...
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... TABLE 1-2: PIC16LF1904/6/7 PINOUT DESCRIPTION (CONTINUED) Name Function (2) RD0 /COM3 RD0 COM3 (2) RD1 /SEG27 RD1 SEG27 (2) RD2 /SEG28 RD2 SEG28 (2) RD3 /SEG16 RD3 SEG16 (2) RD4 /SEG17 RD4 SEG17 (2) RD5 /SEG18 RD5 SEG18 (2) RD6 /SEG19 RD6 SEG19 (2) RD7 /SEG20 RD7 SEG20 (2) RE0 ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 18 Preliminary 2011 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 21.0 “Instruction Set Summary” details. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Saving”, for more details. for more Preliminary DS41569A-page 19 ...
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... PIC16LF1904/6/7 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration Configuration Configuration Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg 15 15 Instruction Instruction Instruction Decode and Decode & Decode & Control Control Control CLKIN Timing Timing Timing ...
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... The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. implemented for the PIC16LF1904/6/7 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 3-1, and 3-2) ...
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... PIC16LF1904/6/7 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16LF1904 PC<14:0> CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector Page 0 On-chip Program Memory Page 1 Rollover to Page 0 Rollover to Page 1 DS41569A-page 22 FIGURE 3-2: CALL, CALLW ...
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... Example 3-2 demonstrates access- ing the program memory via an FSR. The HIGH directive will set bit<7> label points to a location in program memory. 2011 Microchip Technology Inc. PIC16LF1904/6/7 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 RETLW DATA1 ...
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... PIC16LF1904/6/7 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): • 12 core registers • 20 Special Function Registers (SFR) • bytes of General Purpose RAM (GPR) • 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘ ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2011 Microchip Technology Inc. PIC16LF1904/6/7 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...
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... Bank Offset 00h 0Bh 0Ch 1Fh 20h Section 3.5.2 6Fh 70h 7Fh 3.2.5 DEVICE MEMORY MAPS The memory maps for PIC16LF1904/6/7 are as shown in Table 3-3. Preliminary BANKED MEMORY PARTITIONING Memory Region Core Registers (12 bytes) Special Function Registers (20 bytes maximum) General Purpose RAM ...
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... TABLE 3-3: PIC16LF1904/6/7 MEMORY MAP BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh (1) (1) 00Fh PORTD ...
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... TABLE 3-3: PIC16LF1904/6/7 MEMORY MAP (CONTINUED) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 46Fh 4EFh 56Fh 470h 4F0h ...
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... TABLE 3-3: PIC16LF1904/6/7 MEMORY MAP (CONTINUED) BANK 15 780h Core Registers (Table 3-2) 78Bh 78Ch Unimplemented Read as ‘0’ 790h LCDCON 791h LCDPS 792h LCDREF 793h LCDCST 794h LCDRL 795h — 796h — 797h LCDSE0 798h LCDSE1 799h LCDSE2 79Ah LCDSE3 79Bh ...
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... PIC16LF1904/6/7 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-4 addressed from any Bank. TABLE 3-4: CORE FUNCTION REGISTERS SUMMARY Addr Name Bit 7 Bit 6 Bank 0-31 x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory INDF0 x80h ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2: PIC16LF1904/7 only. 3: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2: PIC16LF1904/7 only. 3: DS41569A-page 32 Bit 5 Bit 4 Bit 3 Bit 2 — — — ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2: PIC16LF1904/7 only. 3: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... Top of Stack High byte x = unknown unchanged value depends on condition unimplemented, read as ‘0’ reserved. Legend: Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Note 1: Unimplemented, read as ‘1’. 2: PIC16LF1904/7 only. 3: DS41569A-page 34 Bit 5 Bit 4 Bit 3 Bit 2 SEG5 SEG4 ...
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... PCL register, all 15 bits of the program counter will change to the values con- tained in the PCLATH register and those being written to the PCL register. 2011 Microchip Technology Inc. PIC16LF1904/6/7 3.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a ...
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... PIC16LF1904/6/7 3.4 Stack All devices have a 16-level x 15-bit wide hardware stack (refer to Figure 3-5). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution ...
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... FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL 2011 Microchip Technology Inc. PIC16LF1904/6/7 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 ...
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... PIC16LF1904/6/7 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register ...
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... FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: 2011 Microchip Technology Inc. PIC16LF1904/6/7 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory ...
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... PIC16LF1904/6/7 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR ...
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... Location Select 0x2000 0x29AF 2011 Microchip Technology Inc. PIC16LF1904/6/7 3.5.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 42 Preliminary 2011 Microchip Technology Inc. ...
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... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. PIC16LF1904/6/7 by device Preliminary DS41569A-page 43 ...
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... PIC16LF1904/6/7 REGISTER 4-1: CONFIGURATION WORD 1 U-1 — bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 7 Legend Readable bit P = Programmable bit ‘0’ = Bit is cleared ‘1’ = Bit is set bit 13-12 Unimplemented: Read as ‘1’ bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. ...
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... Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 4 kW Flash memory (PIC16LF1904 only Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control 00 = 000h to FFFh write-protected, no addresses may be modified by PMCON control ...
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... PIC16LF1904/6/7 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1 ...
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... PIC16LF1906 10 1100 011 PIC16LF1907 10 1100 010 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above). 2011 Microchip Technology Inc. PIC16LF1904/6 DEV<8:3> REV<4:0> Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit DEVICEID< ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 48 Preliminary 2011 Microchip Technology Inc. ...
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... External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR Enable 2011 Microchip Technology Inc. PIC16LF1904/6/7 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. PWRT Zero 72 ms LFINTOSC PWRTEN Preliminary Device Reset DS41569A-page 49 ...
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... PIC16LF1904/6/7 5.1 Power-on Reset (POR) The POR circuit holds the device in Reset until V reached an acceptable level for minimum operation. Slow rising V , fast operating speeds or analog DD performance may require greater than minimum V The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met ...
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... Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2011 Microchip Technology Inc. PIC16LF1904/6/7 (1) T PWRT < T PWRT PWRT (1) T ...
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... PIC16LF1904/6/7 5.3 Low-Power Brown-out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external V When too low of a voltage is detected, the device is held in Reset ...
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... FIGURE 5-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC16LF1904/6/7 T PWRT T MCLR T OST Preliminary DS41569A-page 53 ...
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... PIC16LF1904/6/7 5.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC16LF1904/6/7 The PCON register bits are shown in R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT RMCLR Bit is set by hardware U = Unimplemented bit, read as ‘ ...
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... PIC16LF1904/6/7 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 BORCON SBOREN BORFS PCON STKOVF STKUNF STATUS — — WDTCON — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS41569A-page 56 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... The INTOSC internal oscillator block produces a low and high-frequency clock source, LFINTOSC and HFINTOSC (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these two clock sources. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Figure 6-1 designated Preliminary DS41569A-page 57 ...
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... PIC16LF1904/6/7 FIGURE 6-1: SIMPLIFIED PIC CLKIN EC CLKIN Secondary Oscillator T1CKI/ Secondary T1OSO Oscillator (T1OSC) T1OSI Internal Oscillator IRCF<3:0> Start-up Control Logic 16 MHz Primary Osc Start-Up Osc LF-INTOSC (31 kHz) DS41569A-page 58 ® MCU CLOCK SOURCE BLOCK DIAGRAM Secondary Clock 4 4 HF-16 MHz /1 1111 ...
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... High power, 4-20 MHz (FOSC = 11) • Medium power, 0.5-4 MHz (FOSC = 10) • Low power, 0-0.5 MHz (FOSC = 01) 2011 Microchip Technology Inc. PIC16LF1904/6/7 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... PIC16LF1904/6/7 6.2.1.2 Secondary Oscillator The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral opti- mized for timekeeping operations with a 32.768 kHz crystal connected between the T1CKI/T1OSO and T1OSI device pins. The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching ...
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... Microchip Technology Inc. PIC16LF1904/6/7 Following any Reset, the IRCF<3:0> bits Note: of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. The IRCF< ...
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... PIC16LF1904/6/7 FIGURE 6-4: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (WDT disabled) HFINTOSC LFINTOSC 0 IRCF <3:0> System Clock HFINTOSC LFINTOSC (WDT enabled) HFINTOSC LFINTOSC IRCF <3:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <3:0> System Clock ...
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... FOSC<1:0> bits in the Configuration Word 1, or from the internal clock source. The OST does not reflect the status of the secondary oscillator. 2011 Microchip Technology Inc. PIC16LF1904/6/7 6.3.3 SECONDARY OSCILLATOR The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral optimized for timekeeping operations with a 32 ...
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... PIC16LF1904/6/7 6.4 Oscillator Control Registers REGISTER 6-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R/W-0/0 R/W-1/1 — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 000x = 31 kHz LF 001x = 31 ...
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... CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘ 0 ’. Shaded cells are not used by clock sources. Legend: 2011 Microchip Technology Inc. PIC16LF1904/6/7 R-0/q U-0 HFIOFR — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional ...
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... PIC16LF1904/6/7 NOTES: DS41569A-page 66 Preliminary 2011 Microchip Technology Inc. ...
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... Many peripherals produce Interrupts. Refer to the cor- responding chapters for details. FIGURE 7-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IF) PIR1<0> PIRn<7> PIEn<7> 2011 Microchip Technology Inc. PIC16LF1904/6/7 A block diagram of the interrupt logic is shown in Figure 7.1. TMR0IF TMR0IE INTF INTE IOCIF IOCIE ...
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... PIC16LF1904/6/7 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the ...
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... Interrupt GIE PC-1 PC FSR ADDR PC Execute 3 Cycle Instruction at PC Interrupt GIE PC-1 PC FSR ADDR PC Execute 3 Cycle Instruction at PC 2011 Microchip Technology Inc. PIC16LF1904/6/7 Interrupt Sampled during Q1 PC+1 0004h Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 ...
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... PIC16LF1904/6/7 FIGURE 7-3: INT PIN INTERRUPT TIMING CLKIN (3) CLKOUT (4) INT pin (1) INTF (5) GIE INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC – 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 T Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. ...
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... ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Section 8.0 Preliminary DS41569A-page 71 ...
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... PIC16LF1904/6/7 7.6 Interrupt Control Registers 7.6.1 INTCON REGISTER The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 ...
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... Unimplemented: Read as ‘0’ bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt . 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 U-0 U-0 TXIE — ...
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... PIC16LF1904/6/7 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 7-3. REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘ ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. PIC16LF1904/6/7 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. ...
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... PIC16LF1904/6/7 7.6.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 7-5. REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘ ...
Page 77
... ADIE PIE2 — — PIR1 TMR1GIF ADIF PIR2 — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF T0CS T0SE PSA RCIE TXIE — ...
Page 78
... PIC16LF1904/6/7 NOTES: DS41569A-page 78 Preliminary 2011 Microchip Technology Inc. ...
Page 79
... Examples of internal circuitry that might be sourcing current include the FVR module. See 13.0 “Fixed Volt- for more information. age Reference (FVR)” 2011 Microchip Technology Inc. PIC16LF1904/6/7 8.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. ...
Page 80
... PIC16LF1904/6/7 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP ...
Page 81
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC16LF1904/6/7 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41569A-page 81 ...
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... PIC16LF1904/6/7 9.1 Independent Clock Source The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1ms. See Section 22.0 “Electrical Specifications” LFINTOSC tolerances. 9.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE< ...
Page 83
... WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 84
... PIC16LF1904/6/7 NOTES: DS41569A-page 84 Preliminary 2011 Microchip Technology Inc. ...
Page 85
... When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. 2011 Microchip Technology Inc. PIC16LF1904/6/7 10.1.1 PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses ...
Page 86
... PIC16LF1904/6/7 TABLE 10-1: FLASH MEMORY ORGANIZATION BY DEVICE Row Erase Device (words) PIC16LF1904/6/7 32 10.2.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. Write the desired address PMADRH:PMADRL register pair. 2. Clear the CFGS bit of the PMCON1 register. 3. Then, set control bit RD of the PMCON1 register. ...
Page 87
... MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16LF1904/6/7 PMADRH,PMADRL PC+3 INSTR ( PMDATH,PMDATL INSTR ( INSTR( INSTR( instruction ignored instruction ignored Forced NOP Forced NOP ...
Page 88
... PIC16LF1904/6/7 10.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write pro- gramming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: • Row Erase • Load program memory write latches • ...
Page 89
... This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. 2011 Microchip Technology Inc. PIC16LF1904/6/7 FIGURE 10-4: FLASH PROGRAM MEMORY ERASE FLOWCHART ...
Page 90
... PIC16LF1904/6/7 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF INTCON,GIE BANKSEL PMADRL MOVF ADDRL,W ...
Page 91
... Microchip Technology Inc. PIC16LF1904/6/7 The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1 ...
Page 92
FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES PMADRH - Row PMADRH<6:0> Address :PMADRL<7:5> Decode ...
Page 93
... Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Write Operation (FREE = 0) Load Write Latches Only (LWLO = 1) 2011 Microchip Technology Inc. PIC16LF1904/6/7 Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Yes Last word to write ? ...
Page 94
... PIC16LF1904/6/7 EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL ...
Page 95
... Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 2011 Microchip Technology Inc. PIC16LF1904/6/7 FIGURE 10-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure x.x) Figure 10-1 ...
Page 96
... PIC16LF1904/6/7 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> but not all addresses are accessible. ...
Page 97
... RAM. This image will be used to verify the data currently stored in Flash program memory. Read Operation (Figure x.x) Figure 10-1 PMDAT = No RAM image ? Fail Yes Verify Operation No Last Word ? Yes End Verify Operation 2011 Microchip Technology Inc. PIC16LF1904/6/7 Preliminary DS41569A-page 97 ...
Page 98
... PIC16LF1904/6/7 10.6 Flash Program Memory Control Registers REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory ...
Page 99
... Unimplemented bit, read as ‘ 1 ’. Note 1: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started ( The LWLO bit is ignored during a program memory erase operation (FREE = 2011 Microchip Technology Inc. PIC16LF1904/6/7 (2) R/W/HC-0/0 R/W/HC-x/q R/W-0/0 FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
Page 100
... PIC16LF1904/6/7 REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 bit 7 Legend Readable bit W = Writable bit S = Bit can only be set x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register ...
Page 101
... A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in 2011 Microchip Technology Inc. PIC16LF1904/6/7 FIGURE 11-1: Write LATx Write PORTx Data Bus ...
Page 102
... PIC16LF1904/6/7 11.1 PORTA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin) ...
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... Bit is cleared bit 7-4 LATA<7:0>: RA<7:4> Output Latch Value bits Writes to PORTA are actually written to the corresponding LATA register. Reads from the PORTA register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-x/x R-x/x R/W-x/x RA4 RA3 RA2 U = Unimplemented bit, read as ‘ ...
Page 104
... PIC16LF1904/6/7 REGISTER 11-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 — — ANSA5 bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: Analog Select between Analog or Digital Function on pins RA5, respectively 0 = Digital I/O ...
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... To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. 2011 Microchip Technology Inc. PIC16LF1904/6/7 11.2.2 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The ...
Page 106
... PIC16LF1904/6/7 REGISTER 11-5: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RB<7:0>: PORTB General Purpose I/O Pin bits 1 = Port pin is > Port pin is < ...
Page 107
... TRISB7 TRISB6 WPUB WPUB7 WPUB6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. Legend: 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
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... PIC16LF1904/6/7 11.3 PORTC Registers PORTC is an 8-bit wide bidirectional port. The corresponding data direction register (Register 11-6). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
Page 109
... Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-x/u R/W-x/u R/W-x/u RC4 RC3 RC2 U = Unimplemented bit, read as ‘ ...
Page 110
... PIC16LF1904/6/7 TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 LATC LATC7 LATC6 PORTC RC7 RC6 TRISC TRISC7 TRISC6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Legend: DS41569A-page 110 Bit 5 Bit 4 Bit 3 Bit 2 LATC5 ...
Page 111
... PORTD Registers (PIC16LF1904/7 only) PORTD is a 8-bit wide, bidirectional port. The corresponding data direction register (Register 11-14). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
Page 112
... PIC16LF1904/6/7 REGISTER 11-13: PORTD: PORTD REGISTER R/W-x/u R/W-x/u R/W-x/u RD7 RD6 RD5 bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bits 1 = Port pin is > Port pin is < ...
Page 113
... Bit 6 LATD LATD7 LATD6 PORTD RD7 RD6 TRISD TRISD7 TRISD6 x = unknown unchanged unimplemented locations read as ‘ 0 ’. Shaded cells are not used by PORTD. Legend: PIC16LF1904/7 only. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 LATD5 LATD4 LATD3 LATD2 ...
Page 114
... PIC16LF1904/6/7 11.5 PORTE Registers RE3 is input only, and also functions as MCLR. The MCLR feature can be disabled via a configuration fuse. RE3 also supplies the programming voltage. The TRIS bit for RE3 (TRISE3) always reads ‘1’. REGISTER 11-16: PORTE: PORTE REGISTER U-0 ...
Page 115
... Unimplemented: Read as ‘0’ bit 2-0 LATE<2:0>: PORTE Output Latch Value bits Writes to PORTE are actually written to the corresponding LATE register. Reads from the PORTE register is Note 1: return of actual I/O pin values. PIC16LF1904/7 only. 2: REGISTER 11-19: ANSELE: PORTE ANALOG SELECT REGISTER U-0 U-0 U-0 — ...
Page 116
... WPUE — — unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Legend: Unimplemented, read as ‘1’. Note 1: PIC16LF1904/7 only. 2: DS41569A-page 116 U-0 R/W-1/1 WPUE3 — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 117
... RBx IOCBPx 2011 Microchip Technology Inc. PIC16LF1904/6/7 12.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the interrupt-on-change pins of PORTB expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
Page 118
... PIC16LF1904/6/7 12.6 Interrupt-On-Change Registers REGISTER 12-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 IOCBP7 IOCBP6 IOCBP5 bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge ...
Page 119
... IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB7 TRISB6 TRISB Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 TMR0IE INTE IOCIE TMR0IF ...
Page 120
... PIC16LF1904/6/7 NOTES: DS41569A-page 120 Preliminary 2011 Microchip Technology Inc. ...
Page 121
... HFINTOSC FOSC<2:0> = 100 and IRCF<3:0> = 000x BOREN<1:0> BOR BOREN<1:0> and BORFS = 1 BOREN<1:0> and BORFS = 1 2011 Microchip Technology Inc. PIC16LF1904/6/7 13.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC is routed through two independent amplifiers. Each amplifier can be configured to amplify the reference voltage 2x, to produce the two possible voltage levels ...
Page 122
... PIC16LF1904/6/7 13.3 FVR Control Registers REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 (1) FVREN FVRRDY TSEN bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit ...
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... FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. PIC16LF1904/6/7 FIGURE 14-1: 14.2 Minimum Operating V Minimum Sensing Temperature ...
Page 124
... PIC16LF1904/6/7 NOTES: DS41569A-page 124 Preliminary 2011 Microchip Technology Inc. ...
Page 125
... FVR Buffer1 CHS<4:0> When ADON = 0, all multiplexer inputs are disconnected. Note 1: See ADCON0 register 2: 2011 Microchip Technology Inc. PIC16LF1904/6/7 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ADPREF = 00 ...
Page 126
... PIC16LF1904/6/7 15.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Result formatting 15.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...
Page 127
... FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2011 Microchip Technology Inc. PIC16LF1904/6 DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 16 MHz 8 MHz (2) 125 ns (2) 250 ns (2) (2) 250 ns 500 ns (2) 0.5 s (2) 1.0 ...
Page 128
... PIC16LF1904/6/7 15.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software ...
Page 129
... Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC16LF1904/6/7 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 130
... PIC16LF1904/6/7 15.2.5 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) 2. Configure the ADC module: • Select ADC conversion clock • ...
Page 131
... ADC is disabled and consumes no operating current See Note 1: Section 13.0 “Fixed Voltage Reference (FVR)” See 2: Section 14.0 “Temperature Indicator Module” 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (2) (1) for more information ...
Page 132
... PIC16LF1904/6/7 REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded Left justified. Six Least Significant bits of ADRESL are set to ‘ ...
Page 133
... Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 134
... PIC16LF1904/6/7 REGISTER 15-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u — — — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES< ...
Page 135
... The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. PIC16LF1904/6/7 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 136
... PIC16LF1904/6/7 FIGURE 15-4: ANALOG INPUT MODEL Analog Input pin Rs C PIN Sample/Hold Capacitance Legend: HOLD C = Input Capacitance PIN I = Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Resistance of Sampling Switch Sampling Switch V = Threshold Voltage T Refer to Note 1: Section 22.0 “Electrical Specifications” ...
Page 137
... TRISB TRISB7 TRISB6 FVRCON FVREN FVRRDY x = unknown unchanged, — = unimplemented read as ‘ 0 ’ value depends on condition. Shaded cells are not Legend: used for ADC module. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — ...
Page 138
... PIC16LF1904/6/7 NOTES: DS41569A-page 138 Preliminary 2011 Microchip Technology Inc. ...
Page 139
... T0CKI 1 TMR0SE TMR0CS 2011 Microchip Technology Inc. PIC16LF1904/6/7 16.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...
Page 140
... PIC16LF1904/6/7 16.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. The Watchdog Timer (WDT) uses its own Note: independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS< ...
Page 141
... TRISA TRISA7 TRISA6 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 142
... PIC16LF1904/6/7 NOTES: DS41569A-page 142 Preliminary 2011 Microchip Technology Inc. ...
Page 143
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. PIC16LF1904/6/7 • Gate Value Status • Gate Event Interrupt Figure 17 block diagram of the Timer1 module. ...
Page 144
... PIC16LF1904/6/7 17.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source ...
Page 145
... When switching from asynchronous to synchronous operation possible to produce an additional increment. 2011 Microchip Technology Inc. PIC16LF1904/6/7 17.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...
Page 146
... PIC16LF1904/6/7 17.6.2 TIMER1 GATE SOURCE SELECTION The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register ...
Page 147
... Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. PIC16LF1904/6/7 17.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode ...
Page 148
... PIC16LF1904/6/7 FIGURE 17-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 17-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41569A-page 148 Preliminary 2011 Microchip Technology Inc ...
Page 149
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC16LF1904/6/7 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41569A-page 149 ...
Page 150
... PIC16LF1904/6/7 FIGURE 17-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41569A-page 150 Set by hardware on falling edge of T1GVAL Preliminary 2011 Microchip Technology Inc. ...
Page 151
... Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 152
... PIC16LF1904/6/7 17.10 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 17-2, is used to control Timer1 gate. REGISTER 17-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘ ...
Page 153
... TRISC6 TMR1CS1 TMR1CS0 T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. 2011 Microchip Technology Inc. PIC16LF1904/6/7 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF RCIE TXIE — ...
Page 154
... PIC16LF1904/6/7 NOTES: DS41569A-page 154 Preliminary 2011 Microchip Technology Inc. ...
Page 155
... SPBRGL BRGH BRG16 2011 Microchip Technology Inc. PIC16LF1904/6/7 The EUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length • Address detection in 9-bit mode • ...
Page 156
... PIC16LF1904/6/7 FIGURE 18-2: EUSART RECEIVE BLOCK DIAGRAM RX/DT pin Pin Buffer and Control Baud Rate Generator BRG16 + 1 Multiplier SYNC SPBRGH SPBRGL BRGH BRG16 The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • ...
Page 157
... ANSEL bit. The TXIF transmitter interrupt flag is set Note: when the TXEN enable bit is set. 2011 Microchip Technology Inc. PIC16LF1904/6/7 18.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register ...
Page 158
... PIC16LF1904/6/7 18.1.1.5 TSR Status The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register ...
Page 159
... RX9 SPBRGL SPBRGH TXREG TXSTA CSRC TX9 — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission. Legend: * Page provides register information. PIC16LF1904/7 only. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 bit 0 bit 1 Word Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 160
... PIC16LF1904/6/7 18.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 18-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate ...
Page 161
... CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 2011 Microchip Technology Inc. PIC16LF1904/6/7 18.1.2.7 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set, the EUSART will shift 9 bits into the RSR for each character received ...
Page 162
... PIC16LF1904/6/7 18.1.2.9 Asynchronous Reception Set-up: 1. Initialize the SPBRGH:SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 18.3 “EUSART Baud Rate Generator (BRG)”). 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 3. Enable the serial port by setting the SPEN bit and the RX/DT pin TRIS bit ...
Page 163
... TRISC7 TRISC6 TXSTA CSRC TX9 — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception. Legend: * Page provides register information. PIC16LF1904/7 only. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 Start bit 7/8 bit 7/8 Stop Stop bit ...
Page 164
... PIC16LF1904/6/7 18.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the frequency may drift temperature changes, DD and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind ...
Page 165
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘ ...
Page 166
... PIC16LF1904/6/7 REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 ABDOVF RCIDL — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode Auto-baud timer overflowed ...
Page 167
... Don’t care value of SPBRGH, SPBRGL register pair Legend: 2011 Microchip Technology Inc. PIC16LF1904/6/7 If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock ...
Page 168
... PIC16LF1904/6/7 TABLE 18-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 BAUD1CON ABDOVF RCIDL BAUD2CON ABDOVF RCIDL RCSTA SPEN RX9 SPBRGL SPBRGH TXSTA CSRC TX9 — = unimplemented, read as ‘ 0 ’. Shaded bits are not used by the BRG. Legend: * Page provides register information. ...
Page 169
... Microchip Technology Inc. PIC16LF1904/6/7 SYNC = 0, BRGH = 0, BRG16 = 18.432 MHz F = 16.000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — ...
Page 170
... PIC16LF1904/6/7 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED 8.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) — — — 300 1200 — — — 2400 2404 0.16 207 9600 9615 0.16 51 10417 10417 0.00 47 10417 19.2k 19231 0 ...
Page 171
... Microchip Technology Inc. PIC16LF1904/6 18.432 MHz F = 16.000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) 300.0 0.00 15359 300.0 ...
Page 172
... PIC16LF1904/6/7 18.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “ ...
Page 173
... RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. 2011 Microchip Technology Inc. PIC16LF1904/6/7 18.3.3.1 Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros ...
Page 174
... PIC16LF1904/6/7 FIGURE 18-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2 OSC1 Bit set by user WUE bit RX/DT Line RCIF The EUSART remains in Idle while the WUE bit is set. Note 1: FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 ...
Page 175
... Reg. Empty Flag) SENDB Sampled Here SENDB (send Break control bit) 2011 Microchip Technology Inc. PIC16LF1904/6/7 When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. 18.3.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways ...
Page 176
... PIC16LF1904/6/7 18.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry ...
Page 177
... RX/DT pin TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit 2011 Microchip Technology Inc. PIC16LF1904/6/7 4. Disable Receive mode by clearing bits SREN and CREN. 5. Enable Transmit mode by setting the TXEN bit 9-bit transmission is desired, set the TX9 bit. ...
Page 178
... TRISG — — TXREG TXSTA CSRC TX9 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master transmission. Legend: * Page provides register information. PIC16LF1904/7 only. Note 1: DS41569A-page 178 Bit 5 Bit 4 Bit 3 Bit 2 — SCKP BRG16 — — ...
Page 179
... If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. 2011 Microchip Technology Inc. PIC16LF1904/6/7 If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART ...
Page 180
... SPEN RX9 SPBRGL SPBRGH TXSTA CSRC TX9 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception. Legend: * Page provides register information. PIC16LF1904/7 only. Note 1: DS41569A-page 180 bit 1 bit 2 bit 3 bit 4 Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 181
... Transmission”), except in the “Synchronous Master case of the Sleep mode. 2011 Microchip Technology Inc. PIC16LF1904/6/7 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. The first character will immediately transfer to the TSR register and transmit. ...
Page 182
... TRISC TRISC7 TRISC6 TXREG TXSTA CSRC TX9 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave transmission. Legend: * Page provides register information. PIC16LF1904/7 only. Note 1: DS41569A-page 182 Bit 5 Bit 4 Bit 3 Bit 2 — SCKP BRG16 — — ...
Page 183
... TX9 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception. Legend: * Page provides register information. 2011 Microchip Technology Inc. PIC16LF1904/6/7 18.4.2.4 Synchronous Slave Reception Set-up: 1. Set the SYNC and SPEN bits and clear the CSRC bit ...
Page 184
... PIC16LF1904/6/7 NOTES: DS41569A-page 184 Preliminary 2011 Microchip Technology Inc. ...
Page 185
... DRIVER MODULE The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16LF1904/6/7 device, the module drives the panels four commons and up to 116 total segments. The LCD module also provides control of the LCD pixel data. ...
Page 186
... The following LCDSEn registers are available: • LCDSE0 SE<7:0> • LCDSE1 SE<15:8> • LCDSE2 SE<23:16> (PIC16LF1904/1907 only) (1) • LCDSE3 SE<28:24> (SE<26:24> Once the module is initialized for the LCD panel, the individual bits of the LCDDATAn registers are cleared/set to represent a clear/dark pixel, respectively: • ...
Page 187
... On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 72 segments. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 U-0 R/W-0/0 R/W-0/0 CS<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit Maximum Number of Pixels PIC16LF1906 PIC16LF1904 (1) 72 116 Preliminary R/W-1/1 R/W-1/1 LMUX<1:0> ...
Page 188
... PIC16LF1904/6/7 REGISTER 19-2: LCDPS: LCD PHASE REGISTER R/W-0/0 R/W-0/0 R-0/0 WFT BIASMD LCDA bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WFT: Waveform Type bit 1 = Type-B phase changes on each frame boundary ...
Page 189
... The VLCD1 pin is connected to the internal bias voltage LCDBIAS1 0 = The VLCD1 pin is not connected bit 0 Unimplemented: Read as ‘0’ Normal pin controls of TRISx and ANSELx are unaffected. Note 1: 2011 Microchip Technology Inc. PIC16LF1904/6/7 U-0 R/W-0/0 R/W-0/0 — VLCD3PE VLCD2PE U = Unimplemented bit, read as ‘0’ ...
Page 190
... PIC16LF1904/6/7 REGISTER 19-4: LCDCST: LCD CONTRAST CONTROL REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LCDCST<2:0>: LCD Contrast Control bits ...
Page 191
... Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark Pixel off (clear) 2011 Microchip Technology Inc. PIC16LF1904/6/7 R/W-0/0 R/W-0/0 R/W-0/0 SEn SEn SEn U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 192
... PIC16LF1904/6/7 19.2 LCD Clock Source Selection The LCD module has 3 possible clock sources: • F /256 OSC • T1OSC • LFINTOSC The first clock source is the system clock divided by 256 (F /256). This divider ratio is chosen to provide OSC about 1 kHz output when the system clock is 8 MHz. ...
Page 193
... So that the user is not forced to place external compo- nents and use up to three pins for bias voltage generation, internal contrast control and an internal reference ladder are provided internally to the PIC16LF1904/6/7. Both of these features may be used in conjunction with the exter- nal VLCD<3:1> pins, to provide maximum flexibility. Refer ...
Page 194
... PIC16LF1904/6/7 19.4 LCD Bias Internal Reference Ladder The internal reference ladder can be used to divide the LCD bias voltage two or three equally spaced voltages that will be supplied to the LCD segment pins. To create this, the reference ladder consists of three matched resistors. Refer to Figure 19-3 ...
Page 195
... COM0 SEG0 COM0-SEG0 2011 Microchip Technology Inc. PIC16LF1904/6/7 The LCDRL register allows switching between two power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the time when the LCD segments transition. ‘B’ Power mode is the remaining time before the segments or commons change again. The LRLAT< ...
Page 196
FIGURE 19-5: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time 32 kHz Clock Ladder Power ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 Control Segment Clock Segment Data ...
Page 197
FIGURE 19-6: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time 32 kHz Clock Ladder Power ‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F Control Segment Clock Segment Data Power Mode ...
Page 198
... PIC16LF1904/6/7 REGISTER 19-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS R/W-0/0 R/W-0/0 R/W-0/0 LRLAP<1:0> LRLBP<1:0> bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits ...
Page 199
... The LCD module automatically turns on the Note: Fixed Voltage Reference when needed. 2011 Microchip Technology Inc. PIC16LF1904/6/7 The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST = 111. Whenever the LCD module is inactive (LCDA = 0), the contrast control ladder will be turned off (open) ...
Page 200
... PIC16LF1904/6/7 19.5 LCD Multiplex Types The LCD driver module can be configured into one of four multiplex types: • Static (only COM0 is used) • 1/2 multiplex (COM<1:0> are used) • 1/3 multiplex (COM<2:0> are used) • 1/4 multiplex (COM<3:0> are used) The LMUX<1:0> bit setting of the LCDCON register ...