PIC18F26J13-I/SP Microchip Technology, PIC18F26J13-I/SP Datasheet - Page 94
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PIC18F26J13-I/SP
Manufacturer Part Number
PIC18F26J13-I/SP
Description
28-pin, GP, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SPDIP .300
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F26J13-ISS.pdf
(496 pages)
2.PIC18F26J13-ISS.pdf
(558 pages)
3.PIC18F26J13-ISS.pdf
(12 pages)
Specifications of PIC18F26J13-I/SP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PIC18(L)F2X/4XK22
5.5.3
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom section of Bank 0, this
mode maps the contents from a user defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see
Bank”). An example of Access Bank remapping in this
addressing mode is shown in
FIGURE 5-12:
DS41412D-page 94
Example Situation:
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to
Access RAM (000h-05Fh).
Special File Registers at
F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh can still be addressed
by using the BSR.
ADDWF f, d, a
FSR2H:FSR2L = 120h
the
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
bottom
of
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
the
Figure
Section 5.3.2 “Access
FFFh
000h
100h
120h
17Fh
200h
F00h
F60h
5-12.
Data Memory
Window
Bank 14
Bank 15
through
Bank 0
Bank 1
Bank 1
Bank 2
SFRs
Preliminary
additional commands to the existing PIC18 instruction
Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before.
5.6
Enabling the extended instruction set adds eight
set. These instructions are executed as described in
Section 25.2 “Extended Instruction
PIC18 Instruction Execution and
the Extended Instruction Set
2010 Microchip Technology Inc.
Bank 1 “Window”
Access Bank
SFRs
Set”.
00h
5Fh
60h
FFh
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