PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 140

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
TABLE 10-5:
DS41412D-page 140
RB2/INT2/CTED1/
P1B/SDI2/SDA2/
AN8
RB3/CTED2/P2A/
CCP2/SDO2/
C12IN2-/AN9
RB4/IOC0/P1D/
T5G/AN11
RB5/IOC1/P2B/
P3A/CCP3/T3CKI/
T1G/AN13
Legend:
Note 1:
2:
3:
Pin
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =
CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
Function on PORTD and PORTE for PIC18(L)F4XK22 devices.
PORTB I/O SUMMARY (CONTINUED)
Function
P2B
T3CKI
CCP2
SDO2
C12IN2-
CCP3
SDA2
CTED1
SDI2
CTED2
P1B
P3A
AN11
AN13
IOC0
IOC1
INT2
RB2
AN8
RB3
P2A
AN9
RB4
P1D
T5G
RB5
T1G
(1)(3)
(3)
(1)
(3)
(3)
(2)
(2)
(1)
(2)
Setting
TRIS
0
1
1
1
0
1
0
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1
1
1
ANSEL
Setting
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
Type
Pin
Preliminary
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
I
AN
AN
AN
AN
AN
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
2
C
LATB<2> data output; not affected by analog input.
PORTB<2> data input; disabled when analog input
enabled.
External interrupt 2.
CTMU Edge 1 input.
Enhanced CCP1 PWM output 2.
MSSP2 SPI data input.
MSSP2 I
MSSP2 I
Analog input 8.
LATB<3> data output; not affected by analog input.
PORTB<3> data input; disabled when analog input
enabled.
CTMU Edge 2 input.
Enhanced CCP1 PWM output 1.
Compare 2 output/PWM 2 output.
Capture 2 input.
MSSP2 SPI data output.
Comparators C1 and C2 inverting input.
Analog input 9.
LATB<4> data output; not affected by analog input.
PORTB<4> data input; disabled when analog input
enabled.
Interrupt-on-change pin.
Enhanced CCP1 PWM output 4.
Timer5 external clock gate input.
Analog input 11.
LATB<5> data output; not affected by analog input.
PORTB<5> data input; disabled when analog input
enabled.
Interrupt-on-change pin 1.
Enhanced CCP2 PWM output 2.
Enhanced CCP3 PWM output 1.
Compare 3 output/PWM 3 output.
Capture 3 input.
Timer3 clock input.
Timer1 external clock gate input.
Analog input 13.
2
2
C
C
TM
TM
data output.
data input.
2
C
TM
Description
 2010 Microchip Technology Inc.
=
Schmitt Trigger input with I
2
C.