PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 149

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6
Depending on the particular PIC18(L)F2X/4XK22
device selected, PORTE is implemented in two
different ways.
10.6.1
For PIC18(L)F2X/4XK22 devices, PORTE is a 4-bit
wide port. Three pins (RE0/P3A/CCP3/AN5, RE1/P3B/
AN6 and RE2/CCP5/AN7) are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers. When selected as an analog input, these
pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., disable the output driver).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
TRISE controls the direction of the REx pins, even
when they are being used as analog inputs. The user
must make sure to keep the pins configured as inputs
when using them as analog inputs.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/V
only pin. Its operation is controlled by the MCLRE
Configuration bit. When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with its
operation. Otherwise, it functions as the device’s Master
Clear input. In either configuration, RE3 also functions as
the programming voltage input during programming.
EXAMPLE 10-5:
 2010 Microchip Technology Inc.
CLRF
CLRF
CLRF
MOVLW
MOVWF
Note:
Note:
PORTE Registers
PORTE
LATE
ANSELE ; Configure analog pins
05h
TRISE
PORTE ON 40/44-PIN DEVICES
On a Power-on Reset, RE<2:0> are
configured as analog inputs.
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; for digital only
; Value used to
; initialize data
; direction
; Set RE<0> as input
; RE<1> as output
; RE<2> as input
INITIALIZING PORTE
PP
/RE3) is an input
Preliminary
10.6.2
For PIC18F2XK22 devices, PORTE is only available
when
(MCLR = 0). In these cases, PORTE is a single bit,
input only port comprised of RE3 only. The pin operates
as previously described.
10.6.3
The port RE3 pin has an individually controlled weak
internal pull-up. When set, the WPUE3 (TRISE<7>) bit
enables the RE3 pin pull-up. The RBPU bit of the
INTCON2 register controls pull-ups on both PORTB
and PORTE. When RBPU = 0, the weak pull-ups
become active on all pins which have the WPUE3 or
WPUBx bits set. When set, the RBPU bit disables all
weak pull-ups. The pull-ups are disabled on a Power-
on Reset. When the RE3 port pin is configured as
MCLR,
CONFIG4L<2>, LVP=0), or configured for Low Voltage
Programming, (MCLRE=x and LVP=1), the pull-up is
always enabled and the WPUE3 bit has no effect.
10.6.4
Each PORTE pin is multiplexed with other functions.
The pins, their combined functions and their output
priorities are briefly described here. For additional
information, refer to the appropriate section in this data
sheet.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the higher priority.
Table 10-4
highest to the lowest priority.
Analog input functions, such as ADC, comparator and
SR Latch inputs, are not shown in the priority lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELx registers. Digital
output functions may control the pin when it is in Analog
mode with the priority shown below.
PIC18(L)F2X/4XK22
Master
PORTE ON 28-PIN DEVICES
RE3 WEAK PULL-UP
PORTE OUTPUT PRIORITY
lists the PORTE pin functions from the
(CONFIG3H<7>,
Clear
functionality
MCLRE=1
DS41412D-page 149
is
disabled
and