PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 178

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
14.1
The Capture mode function described in this section is
identical for all CCP and ECCP modules available on
this device family.
Capture mode makes use of the 16-bit Timer
resources, Timer1, Timer3 and Timer5. The timer
resources for each CCP capture function are
independent and are selected using the CCPTMRS0
and CCPTMRS1 registers. When an event occurs on
the CCPx pin, the 16-bit CCPRxH:CCPRxL register
pair captures and stores the 16-bit value of the
TMRxH:TMRxL register pair, respectively. An event is
defined as one of the following and is configured by the
CCPxM<3:0> bits of the CCPxCON register:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the corresponding Interrupt
Request Flag bit CCPxIF of the PIR1, PIR2 or PIR4
register is set. The interrupt flag must be cleared in
software. If another capture occurs before the value in
the CCPRxH:CCPRxL register pair is read, the old
captured value is overwritten by the new captured
value.
TABLE 14-2:
14.1.2
The 16-bit Timer resource must be running in Timer
mode or Synchronized Counter mode for the CCP
module to use the capture feature. In Asynchronous
Counter mode, the capture operation may not work.
See
Control”
Timers.
DS41412D-page 178
Legend:
CCP OUTPUT
Section 12.0 “Timer1/3/5 Module with Gate
CCP2
CCP3
Capture Mode
for more information on configuring the 16-bit
*
TIMER1 MODE RESOURCE
= Default
CCP PIN MULTIPLEXING
CONFIG 3H Control Bit
CCP2MX
CCP3MX
Bit Value
Preliminary
1
0
0
1
(*)
(*)
PIC18(L)F2XK22 I/O pin
Figure 14-1
operation.
FIGURE 14-1:
14.1.1
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Some CCPx outputs are multiplexed on a couple of
pins.
multiplexing. Selection of the output pin is determined
by the CCPxMX bits in Configuration register 3H
(CONFIG3H). Refer to
14.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIE1, PIE2 or PIE4
register clear to avoid false interrupts. Additionally, the
user should clear the CCPxIF interrupt flag bit of the
PIR1, PIR2 or PIR4 register following any change in
Operating mode.
CCPx
pin
Note:
Note:
System Clock (F
Table 14-2
RB3
RC1
RC6
RB5
Edge Detect
Prescaler
CCP PIN CONFIGURATION
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
SOFTWARE INTERRUPT MODE
Clocking the 16-bit Timer resource from
the system clock (F
used in Capture mode. In order for
Capture mode to recognize the trigger
event on the CCPx pin, the Timer resource
must be clocked from the instruction clock
(F
 1, 4, 16
shows a simplified diagram of the Capture
and
OSC
CCPxM<3:0>
OSC
/4) or from an external clock source.
)
shows
Set Flag bit CCPxIF
(PIR1/2/4 register)
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Register 24-4
 2010 Microchip Technology Inc.
PIC18(L)F4XK22 I/O pin
the
Capture
Enable
OSC
TMR1/3/5H TMR1/3/5L
CCPRxH
CCP
) should not be
for more details.
RB3
RC1
RE0
RB5
output
CCPRxL
pin