PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 261

64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE

PIC18F46K22-I/MV

Manufacturer Part Number
PIC18F46K22-I/MV
Description
64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F46K22-I/MV

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Number Of Programmable I/os
36
Number Of Timers
3 x 8-bit. 4 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REGISTER 15-6:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
Master mode:
bit 7-0
10-Bit Slave mode — Most Significant Address byte:
bit 7-3
bit 2-1
bit 0
10-Bit Slave mode — Least Significant Address byte:
bit 7-0
7-Bit Slave mode:
bit 7-1
bit 0
R/W-0
ADD<7:0>: Baud Rate Clock Divider bits
SCLx pin clock period = ((ADD<7:0> + 1) *4)/F
Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I
are compared by hardware and are not affected by the value in this register.
ADD<2:1>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
ADD<7:0>: Eight Least Significant bits of 10-bit address
ADD<7:1>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
R/W-0
SSPXADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0
R/W-0
2
Preliminary
C specification and must be equal to ‘11110’. However, those bits
ADD<7:0>
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
OSC
R/W-0
PIC18(L)F2X/4XK22
R/W-0
R/W-0
2
C MODE)
DS41412D-page 261
R/W-0
bit 0

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