PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 330

64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE

PIC18F46K22-I/MV

Manufacturer Part Number
PIC18F46K22-I/MV
Description
64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet

Specifications of PIC18F46K22-I/MV

Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Number Of Programmable I/os
36
Number Of Timers
3 x 8-bit. 4 x 16-bit
Operating Supply Voltage
1.8 V to 5.5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18(L)F2X/4XK22
REGISTER 19-2:
DS41412D-page 330
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-5
bit 4
bit 3-2
bit 1
bit 0
EDG2POL
R/W-0
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 programmed for a positive edge response
0 = Edge 2 programmed for a negative edge response
EDG2SEL<1:0>: Edge 2 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = ECCP1 Special Event Trigger
00 = ECCP2 Special Event Trigger
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 programmed for a positive edge response
0 = Edge 1 programmed for a negative edge response
EDG1SEL<1:0>: Edge 1 Source Select bits
11 = CTED1 pin
10 = CTED2 pin
01 = ECCP1 Special Event Trigger
00 = ECCP2 Special Event Trigger
EDG2STAT: Edge 2 Status bit
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
EDG1STAT: Edge 1 Status bit
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred
R/W-0
EDG2SEL<1:0>
CTMUCONL: CTMU CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
R/W-0
EDG1POL
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EDG1SEL1
R/W-0
EDG1SEL0
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
EDG2STAT
R/W-0
EDG1STAT
R/W-0
bit 0

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