PIC18F46K22-I/MV Microchip Technology, PIC18F46K22-I/MV Datasheet - Page 47

• Manufacturer Part Number: PIC18F46K22-I/MV
• Description: 64KB, Flash, 3968bytes-RAM,8-bit Family,nanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K22-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 30x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Number Of Programmable I/os: 36
• Number Of Timers: 3 x 8-bit. 4 x 16-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.0
PIC18(L)F2X/4XK22 devices offer a total of seven
operating modes for more efficient power manage-
ment. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery-powered
devices).
There are three categories of power-managed modes:
• Run modes
• Idle modes
• Sleep mode
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block). The Sleep mode does not use a clock source.
The power-managed modes include several power-
saving features offered on previous PIC
devices. One of the clock switching features allows the
controller to use the secondary oscillator (SOSC) in
place of the primary oscillator. Also included is the Sleep
mode, offered by all PIC
all device clocks are stopped.
3.1
Selecting a power-managed mode requires two
decisions:
• Whether or not the CPU is to be clocked
• The selection of a clock source
The IDLEN bit (OSCCON<7>) controls CPU clocking,
while the SCS<1:0> bits (OSCCON<1:0>) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table
TABLE 3-1:
 2010 Microchip Technology Inc.
Sleep
PRI_RUN
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
Note 1:
Mode
3-1.
2:
POWER-MANAGED MODES
Selecting Power-Managed Modes
IDLEN reflects its value when the SLEEP instruction is executed.
Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.
IDLEN
POWER-MANAGED MODES
N/A
N/A
N/A
0
1
1
1
OSCCON Bits
(1)
®
microcontroller devices, where
SCS<1:0>
N/A
00
01
1x
00
01
1x
®
microcontroller
Clocked
Clocked
Clocked
CPU
Module Clocking
Off
Off
Off
Off
Preliminary
Peripherals
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
Off
3.1.1
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the FOSC<3:0>
• the secondary clock (the SOSC oscillator)
• the internal oscillator block
3.1.2
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. Refer to
Section 2.9 “Clock Switching”
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
Configuration bits
PIC18(L)F2X/4XK22
None – All clocks are disabled
Primary – LP, XT, HS, RC, EC and Internal
Oscillator Block
This is the normal full-power execution mode.
Secondary – SOSC Oscillator
Internal Oscillator Block
Primary – LP, XT, HS, HSPLL, RC, EC
Secondary – SOSC Oscillator
Internal Oscillator Block
Available Clock and Oscillator Source
CLOCK SOURCES
ENTERING POWER-MANAGED
MODES
(2)
.
(2)
(2)
for more information.
DS41412D-page 47