PIC18F87K90-E/PT Microchip Technology, PIC18F87K90-E/PT Datasheet - Page 487
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F87K90-E/PT
Manufacturer Part Number
PIC18F87K90-E/PT
Description
128kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm TR
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F66K90-IMR.pdf
(570 pages)
Specifications of PIC18F87K90-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F87K90-E/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F87K90-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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SUBLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
2009-2011 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
W
C
W
C
Z
N
W
C
W
C
Z
N
W
C
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
literal ‘k’
Subtract W from Literal
SUBLW k
0 k 255
k – (W) W
N, OV, C, DC, Z
W is subtracted from the 8-bit
literal ‘k’. The result is placed in W.
1
1
SUBLW
SUBLW
SUBLW
Read
Q2
0000
01h
?
01h
1
0
0
02h
?
00h
1
1
0
03h
?
FFh
0
0
1
; result is positive
; result is zero
; result is negative
; (2’s complement)
02h
02h
02h
1000
Process
Data
Q3
kkkk
Write to
Q4
W
kkkk
PIC18F87K90 FAMILY
SUBWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
Q1
Subtract W from f
SUBWF
0 f 255
d [ 0,1 ]
a [ 0,1 ]
(f) – (W) dest
N, OV, C, DC, Z
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘ 0 ’, the
result is stored in W. If ‘d’ is ‘ 1 ’, the result
is stored back in register ‘f’.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
0101
SUBWF
SUBWF
SUBWF
Read
Q2
3
2
?
1
2
1
0
0
2
2
?
2
0
1
1
0
1
2
?
FFh ;(2’s complement)
2
0
0
1
f {,d {,a}}
; result is positive
; result is zero
; result is negative
11da
REG, 1, 0
REG, 0, 0
REG, 1, 0
Process
Data
Q3
DS39957D-page 487
for details.
ffff
destination
Write to
Q4
ffff
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