PIC24F16KA302-E/SP Microchip Technology, PIC24F16KA302-E/SP Datasheet - Page 193
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PIC24F16KA302-E/SP
Manufacturer Part Number
PIC24F16KA302-E/SP
Description
16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 28 SPDIP .300in
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet
1.PIC24F16KA301T-ISO.pdf
(320 pages)
Specifications of PIC24F16KA302-E/SP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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REGISTER 19-2:
2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-10
bit 9-8
bit 7-0
Note 1:
PWCEN
R/W-0
U-0
—
2:
The RTCPWC register is only affected by a POR.
When a new value is written to these register bits, the Seconds Value register should also be written to
properly reset the clock prescalers in the RTCC.
PWCEN: Power Control Enable bit
1 = Power control is enabled
0 = Power control is disabled
PWCPOL: Power Control Polarity bit
PWCCPRE: Power Control Control/Stability Prescaler bits
PWCSPRE: Power Control Sample Prescaler bits
RTCCLK<1:0>: RTCC Clock Select bits
Determines the source of the internal RTCC clock, which is used for all RTCC timer operations.
00 = External Secondary Oscillator (SOSC)
01 = Internal LPRC oscillator
10 = External power line source – 50 Hz
11 = External power line source – 60 Hz
RTCOUT<1:0>: RTCC Output Select bits
Determines the source of the RTCC pin output.
00 = RTCC alarm pulse
01 = RTCC seconds clock
10 = RTCC clock
11 = Power control
Unimplemented: Read as ‘0’
1 = Power control output is active-high
0 = Power control output is active-low
1 = PWC stability window clock is divide-by-2 of source RTCC clock
0 = PWC stability window clock is divide-by-1 of source RTCC clock
1 = PWC sample window clock is divide-by-2 of source RTCC clock
0 = PWC sample window clock is divide-by-1 of source RTCC clock
PWCPOL
R/W-0
U-0
—
RTCPWC: RTCC CONFIGURATION REGISTER 2
W = Writable bit
‘1’ = Bit is set
PWCCPRE
R/W-0
U-0
—
PWCSPRE
R/W-0
U-0
—
PIC24FV32KA304 FAMILY
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RTCCLK1
R/W-0
U-0
—
(2)
RTCCLK0
R/W-0
U-0
—
(1)
(2)
x = Bit is unknown
RTCOUT1
R/W-0
U-0
—
DS39995B-page 193
RTCOUT0
R/W-0
U-0
—
bit 0
bit 8
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