PIC24HJ12GP202-E/SP Microchip Technology, PIC24HJ12GP202-E/SP Datasheet
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... Microchip Technology Inc. PIC24HJ12GP201/202 High-Performance, 16-bit Microcontrollers Preliminary Data Sheet DS70282D ...
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... PICDEM, PICDEM.net, PICtail, PIC Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Four processor exceptions On-Chip Flash and SRAM: • Flash program memory (12 Kbytes) • Data SRAM (1024 bytes) • Boot and General Security for Program Flash © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • ...
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... Fully static design • 3.3V (±10%) operating voltage • Industrial and extended temperature • Low power consumption Packaging: • 18-pin SDIP/SOIC • 28-pin SDIP/SOIC/QFN/SSOP Note: See Table 1 for the exact peripheral features per device. Preliminary © 2009 Microchip Technology Inc. ...
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... The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ12GP201/202 CONTROLLER FAMILIES Device PIC24HJ12GP201 PIC24HJ12GP202 Note 1: Only two out of three timers are remappable. 2: Only two out of three interrupts are remappable. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 ...
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... CAP DDCORE 10 19 Vss (1) /CN1/RB4 TDO/SDA1/RP9 11 18 TCK/SCL1/RP8 INT0/RP7 16 (1) /CN27/RB5 ASCL1/RP6 14 15 Preliminary = Pins are tolerant /CN11/RB15 /CN12/RB14 /CN21/RB9 /CN22/RB8 /CN23/RB7 = Pins are tolerant (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN23/RB7 (1) /CN24/RB6 © 2009 Microchip Technology Inc. ...
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... Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 PIC24HJ12GP202 externally. Preliminary = Pins are tolerant ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70282D-page 6 Preliminary © 2009 Microchip Technology Inc. ...
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... Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ12GP201/202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 (MCU) Preliminary DS70282D-page 7 ...
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... DS70282D-page 8 Data Bus Data Latch X RAM Address Loop Latch Control Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support 16-bit ALU MCLR UART1 CNx SPI1 I2C1 Preliminary PORTA PORTB 16 Remappable Pins © 2009 Microchip Technology Inc. ...
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... ST No Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for analog modules. This pin must be connected at all times. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input O = Output Preliminary P = Power I = Input © 2009 Microchip Technology Inc. ...
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... ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2009 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...
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... Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2-2, it EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR PIC24H JP C and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. is ...
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... REAL ICE™ In-Circuit Emulator User's Guide” DS51616 ® • “Using MPLAB REAL ICE™ In-Circuit Emulator” (poster) DS51749 © 2009 Microchip Technology Inc. 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary Section 8.0 “ ...
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... DS70282D-page 14 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternately, connect 10k resistor to V unused pins and drive the output to logic low. Preliminary © 2009 Microchip Technology Inc ...
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... A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model PIC24HJ12GP201/202 is shown in Figure 3-2. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 3.1 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). ...
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... Control Signals to Various Blocks DS70282D-page 16 X Data Bus Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support Preliminary 16-bit ALU 16 To Peripheral Modules © 2009 Microchip Technology Inc. ...
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... FIGURE 3-2: PIC24HJ12GP201/202 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM PC0 0 Program Space Visibility Page Address ...
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... The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS70282D-page 18 U-0 U-0 — — (2) R-0 R/W-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W bit 0 © 2009 Microchip Technology Inc. ...
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... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
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... The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. Preliminary © 2009 Microchip Technology Inc. ...
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... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY FOR PIC24HJ12GP201/202 DEVICES © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 4.1 Program Address Space The program PIC24HJ12GP201/202 devices is 4M instructions ...
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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. least significant word (lsw Instruction Width Preliminary devices reserve the PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2009 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or translating from 8-bit MCU code ...
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... Optionally Mapped into Program Memory 0xFFFF DS70282D-page 24 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 0x1FFFF 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2009 Microchip Technology Inc. ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ12GP202 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 CN30IE CN29IE — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — — ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — — ...
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TABLE 4-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
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... RPINR21 06AA — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-12: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ12GP202 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — ...
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TABLE 4-14: ADC1 REGISTER MAP FOR PIC24HJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... TABLE 4-15: ADC1 REGISTER MAP FOR PIC24HJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD ...
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... ODCA 02C6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-17: PORTB REGISTER MAP FOR PIC24HJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C8 TRISB15 TRISB14 TRISB13 ...
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TABLE 4-19: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
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... PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 4.2.6 DATA RAM PROTECTION FEATURE The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...
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... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Preliminary © 2009 Microchip Technology Inc. ...
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... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 4.4.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
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... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70282D-page 38 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2009 Microchip Technology Inc. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2009 Microchip Technology Inc. ...
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... Using 1/0 Table Instruction User/Configuration Space Select © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ instructions (192 bytes sin- gle program memory word, and erase program mem- ory in blocks or ‘ ...
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... Operations” for further details. Preliminary stalls (waits) until the PROGRAMMING TIME T )% × FRC Accuracy FRC Tuning 11064 Cycles = × × 0.05 1 0.00375 – 11064 Cycles = × × 0.05 – 1 0.00375 – the user application must to Section 5.3 “Programming © 2009 Microchip Technology Inc. ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 U-0 — — ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS70282D-page 44 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2009 Microchip Technology Inc. ...
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... DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Any active source of Reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state, and some are unaffected. ...
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... SWDTEN bit setting. DS70282D-page 48 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 (1) (CONTINUED) ...
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... Preliminary ) after a PWRT ensures that the system PWRT for more FSCM Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2009 Microchip Technology Inc. ...
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... BOR BOR extension time 100 μs maximum T BOR T Programmable 0-128 ms nominal PWRT power-up time delay 900 μs maximum T Fail-safe Clock FSCM Monitor Delay © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Vbor V BOR T BOR 3 T PWRT T OSCD Reset Time has elapsed. POR ensures the voltage regulator output becomes stable ...
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... V ) for proper DD DD BOR crosses V threshold and the delay BOR ensures the voltage BOR ) is programmed by PWRT Reset Timer Value Select bits in the POR Configuration + initiated each time V BOR PWRT DD trip point. BOR V BOR V BOR V BOR © 2009 Microchip Technology Inc. ...
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... Watchdog Reset. Refer to “Watchdog Timer (WDT)” for more information on Watchdog Reset. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 6.7 Trap Conflict Reset If a lower-priority hard trap occurs while a higher-prior- ity trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive ...
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... MCLR Reset RESET instruction WDT Time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR Preliminary Cleared by: POR, BOR POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, CLRWDT instruction, POR, BOR POR, BOR POR, BOR © 2009 Microchip Technology Inc. ...
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... PIC24HJ12GP201/202 devices implement unique interrupts and 4 nonmaskable traps. These are summarized in Table 7-1 and Table 7-2. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1 ...
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... Note 1: See Table 7-1 for the list of implemented interrupt vectors. DS70282D-page 56 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24HJ12GP201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
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... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2009 Microchip Technology Inc. ...
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... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 7.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt ...
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... The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15> DS70282D-page 60 (1) U-0 U-0 — — (3) R-0 R/W-0 ( Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2009 Microchip Technology Inc. ...
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... CPU interrupt priority level is greater than CPU interrupt priority level less Note 1: For complete register details, see Register 3-2: “CORCON: Core Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 ...
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... Unimplemented: Read as ‘0’ DS70282D-page 62 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — ...
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... Interrupt request has not occurred DS70282D-page 64 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282D-page 65 ...
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... Interrupt request has not occurred DS70282D-page 66 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
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... Interrupt request not enabled DS70282D-page 68 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282D-page 69 ...
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... Interrupt request not enabled DS70282D-page 70 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70282D-page 72 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70282D-page 74 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70282D-page 76 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — ...
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... Unimplemented: Read as ‘0’ DS70282D-page 78 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 ...
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... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70282D-page 80 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
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... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
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... PIC24HJ12GP201/202 NOTES: DS70282D-page 82 Preliminary © 2009 Microchip Technology Inc. ...
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... SOSCI Note 1: See Figure 8-2 for PLL details the Oscillator is used with modes, an external parallel resistor with the value of 1 MΩ must be connected. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 • An on-chip PLL to scale the internal operating frequency to the required system clock frequency • ...
Page 86
... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F ’ is given by Equation 8-2. OSC Preliminary © 2009 Microchip Technology Inc. Configuration bits, is divided OSC ) and the ...
Page 87
... Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 EQUATION 8-3: F ------------- 0.8-8.0 MHz ...
Page 88
... PLL modes. DS70282D-page 86 (1) R-0 U-0 R/W-y — NOSC<2:0> U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary © 2009 Microchip Technology Inc. R/W-y R/W-y (2) bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 89
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 (1) ...
Page 90
... Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70282D-page 88 R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...
Page 92
... FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. DS70282D-page 90 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 93
... COSC status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 valid clock switch has been initiated, the LOCK (OSCCON< ...
Page 94
... Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. DS70282D-page 92 Preliminary © 2009 Microchip Technology Inc. ...
Page 95
... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 9.2 Instruction-Based Power-Saving Modes PIC24HJ12GP201/202 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 96
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible © 2009 Microchip Technology Inc. ...
Page 97
... ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 U-0 ...
Page 98
... Output Compare 1 module is enabled DS70282D-page 96 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown ...
Page 99
... CK WR Port Data Latch Read LAT Read Port © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled ...
Page 100
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary © 2009 Microchip Technology Inc. ...
Page 101
... The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or output is being mapped. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...
Page 102
... OC1 Output Enable OC2 Output Enable Default U1TX Output U1RTS Output 4 OC1 Output OC2 Output Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> Output Enable RPn Output Data 18 19 © 2009 Microchip Technology Inc. ...
Page 103
... IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 RPn tied to default port pin 00000 RPn tied to UART1 Transmit ...
Page 104
... Unimplemented: Read as ‘0’ DS70282D-page 102 R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary R/W-1 R/W-1 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 105
... INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 INT2R< ...
Page 106
... Input tied to RP1 00000 = Input tied to RP0 DS70282D-page 104 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 107
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R< ...
Page 108
... Input tied to RP1 00000 = Input tied to RP0 DS70282D-page 106 R/W-1 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 109
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 OCFAR< ...
Page 110
... Input tied to RP1 00000 = Input tied to RP0 DS70282D-page 108 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 111
... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R< ...
Page 112
... Input tied to RP0 DS70282D-page 110 U-0 U-0 — — R/W-1 R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 113
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 ...
Page 114
... Bit is cleared R/W-0 R/W-0 R/W-0 RP7R<4:0> R/W-0 R/W-0 R/W-0 RP6R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 115
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 10-2 for peripheral function numbers) © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 ...
Page 116
... Bit is cleared R/W-0 R/W-0 R/W-0 RP15R<4:0> R/W-0 R/W-0 R/W-0 RP14R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 117
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the source ...
Page 118
... Unimplemented: Read as ‘0’ DS70282D-page 116 U-0 U-0 — — R/W-0 U-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 119
... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an generated with the Timer3 interrupt flags. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 12.1 32-bit Operation To configure the Timer2/3 feature for 32-bit operation: 1. Set the corresponding T32 control bit. ...
Page 120
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70282D-page 118 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2009 Microchip Technology Inc. ...
Page 121
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70282D-page 119 ...
Page 122
... Unimplemented: Read as ‘0’ DS70282D-page 120 U-0 U-0 — — R/W-0 R/W-0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 123
... Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T2CON<3>) register, these bits have no effect. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 (1) — ...
Page 124
... PIC24HJ12GP201/202 NOTES: DS70282D-page 122 Preliminary © 2009 Microchip Technology Inc. ...
Page 125
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 • Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at ICx pin ...
Page 126
... Input capture module turned off DS70282D-page 124 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... TMR3 TMR2 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 value matches the compare register value. The Output Compare module generates either a single output pulse or a sequence of output pulses, by changing the state of the output pin on the compare match events. The Output Compare module can also generate interrupts on compare match events ...
Page 128
... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match Preliminary — © 2009 Microchip Technology Inc. ...
Page 129
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 130
... PIC24HJ12GP201/202 NOTES: DS70282D-page 128 Preliminary © 2009 Microchip Technology Inc. ...
Page 131
... SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Each SPI module consists of a 16-bit shift register, SPIxSR (where 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates status conditions ...
Page 132
... DS70282D-page 130 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 133
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 ...
Page 134
... Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. DS70282D-page 132 (3) (3) Preliminary © 2009 Microchip Technology Inc. ...
Page 135
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 136
... PIC24HJ12GP201/202 NOTES: DS70282D-page 134 Preliminary © 2009 Microchip Technology Inc. ...
Page 137
... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 16.1 Operating Modes The hardware fully implements all the master and slave 2 functions of the I C Standard and Fast mode specifications, as well as 7-bit and 10-bit addressing ...
Page 138
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2009 Microchip Technology Inc. ...
Page 139
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 140
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70282D-page 138 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master master) Preliminary © 2009 Microchip Technology Inc. ...
Page 141
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 R/C-0 HS — ...
Page 142
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70282D-page 140 2 C slave device address byte. Preliminary © 2009 Microchip Technology Inc. ...
Page 143
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 144
... PIC24HJ12GP201/202 NOTES: DS70282D-page 142 Preliminary © 2009 Microchip Technology Inc. ...
Page 145
... UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 • Fully Integrated Baud Rate Generator with 16-bit prescaler • Baud rates ranging from 1 Mbps to 15 bps at 16x mode at 40 MIPS • ...
Page 146
... DS70282D-page 144 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 147
... Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 MODE REGISTER (CONTINUED) ...
Page 148
... STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 149
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70232) in the “PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 STATUS AND CONTROL REGISTER (CONTINUED) x ...
Page 150
... PIC24HJ12GP201/202 NOTES: DS70282D-page 148 Preliminary © 2009 Microchip Technology Inc. ...
Page 151
... There is only one sample-and-hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Depending on the particular device pinout, the ADC can have analog input pins, designated AN0 through AN9. In addition, there are two analog input pins for external voltage reference connections ...
Page 152
... REF REF 2: Channels 1, 2, and 3 are not applicable for the 12-bit mode of operation. DS70282D-page 150 Preliminary (1) ( REF DD REF SS ADC1BUF0 ADC1BUF1 ADC1BUF2 V V REFH REFL SAR ADC ADC1BUFE ADC1BUFF © 2009 Microchip Technology Inc. ...
Page 153
... FIGURE 18-2: ADC BLOCK DIAGRAM FOR PIC24HJ12GP202 DEVICES AN0 AN9 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V - REF CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN6 AN9 V - REF CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 AN7 V - REF CH123NA CH123NB AN2 AN5 ...
Page 154
... Note 1: Refer to Figure 8-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, F the clock source frequency See the ADC electrical characteristics for the exact RC clock value. DS70282D-page 152 AD1CON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 = 1/F . OSC OSC Preliminary AD1CON3<15> equal to OSC © 2009 Microchip Technology Inc. ...
Page 155
... SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> Samples multiple channels individually in sequence © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — ...
Page 156
... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in prog- ress. Automatically cleared by hardware at start of a new conversion. DS70282D-page 154 Preliminary © 2009 Microchip Technology Inc. ...
Page 157
... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — ...
Page 158
... Note 1: This bit only used if AD1CON1<SSRC> This bit is not used if AD1CON3<ADRC> DS70282D-page 156 R/W-0 R/W-0 R/W-0 (1) SAMC<4:0> R/W-0 R/W-0 R/W-0 (2) ADCS<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ( Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 159
... Reserved 00 = Reserved If AD12B = Reserved 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is not connected 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected ...
Page 160
... Reserved 00 = Reserved If AD12B = Reserved 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is not connected 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected ...
Page 161
... Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 PIC24HJ12GP202 devices only: If AD12B = Reserved 0 = Reserved If AD12B = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 © ...
Page 162
... Reserved 00100 = Reserved 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 PIC24HJ12GP202 devices only: 01001 = Channel 0 positive input is AN9 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
Page 163
... Reserved 00100 = Reserved 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 PIC24HJ12GP202 devices only: 01001 = Channel 0 positive input is AN9 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 © ...
Page 164
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1,2) R/W-0 R/W-0 CSS9 CSS8 bit 8 R/W-0 R/W-0 CSS1 CSS0 bit Bit is unknown . REFL (1,2,3) R/W-0 R/W-0 PCFG9 PCFG8 bit 8 R/W-0 R/W-0 PCFG1 PCFG0 bit Bit is unknown SS © 2009 Microchip Technology Inc. ...
Page 165
... FUID2 0xF80016 FUID3 Note 1: Reserved bits read as ‘1’ and must be programmed as ‘1’. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 19.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 0xF80000 ...
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... Allow multiple reconfigurations OSC2 Pin Function bit (except in XT and HS modes OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin Primary Oscillator Mode Select bits 11 = Primary oscillator disabled Crystal Oscillator mode Crystal Oscillator mode (External Clock) mode Preliminary © 2009 Microchip Technology Inc. ...
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... FPWRT<2:0> FPOR JTAGEN FICD ICS<1:0> FICD © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect Watchdog Timer enabled/disabled by user software (LPRC can be ...
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... The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to oper- ate while in Sleep or Idle modes and resets the device (1,2) should V fall below the BOR threshold voltage CAP Preliminary /V . The main purpose of CAP DDCORE © 2009 Microchip Technology Inc. ...
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... CLRWDT Instruction SWDTEN FWDTEN LPRC Clock (divide by N1) WINDIS © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 19.4.2 SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed ...
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... BS = 256 IW 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h GS = 3584 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 768 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 3072 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 1792 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 2048 IW 001FFEh © 2009 Microchip Technology Inc. ...
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... Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 19.8 In-Circuit Debugger ® When MPLAB circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE ...
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... PIC24HJ12GP201/202 NOTES: DS70282D-page 170 Preliminary © 2009 Microchip Technology Inc. ...
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... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: • ...
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... One of 16 source working registers ∈ {W0..W15} Wns WREG W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws Source W register ∈ Wso { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS70282D-page 172 Description Preliminary © 2009 Microchip Technology Inc. ...
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... BTG BTG f,#bit4 BTG Ws,#bit4 10 BTSC BTSC f,#bit4 BTSC Ws,#bit4 11 BTSS BTSS f,#bit4 BTSS Ws,#bit4 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description WREG WREG = f + WREG Wd = lit10 + lit5 WREG + (C) WREG = f + WREG + ( lit10 + lit5 + ( .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND .AND .AND. lit5 ...
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... Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find Bit Change from Left (MSb) Side Find First One from Left (MSb) Side Find First One from Right (LSb) Side Go to address Go to indirect Preliminary © 2009 Microchip Technology Inc Status Flags Words Cycles Affected 1 ...
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... POP.D Wnd POP.S 45 PUSH PUSH f PUSH Wso PUSH.D Wns PUSH.S 46 PWRSAV PWRSAV #lit1 © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description WREG = WREG = .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR .IOR .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f ...
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... WREG – f WREG = WREG – – lit5 – WREG – f – (C) WREG = WREG – f – ( – Wb – ( lit5 – Wb – ( nibble swap byte swap Wn Read Prog<23:16> to Wd<7:0> Preliminary © 2009 Microchip Technology Inc Status Flags Words Cycles Affected 1 2 None 1 2 None ...
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... XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Description Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary ...
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... PIC24HJ12GP201/202 NOTES: DS70282D-page 178 Preliminary © 2009 Microchip Technology Inc. ...
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... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 21.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an instruction © 2009 Microchip Technology Inc. ...
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... REAL ICE offers significant advantages over competi- tive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 21.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
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... IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary © 2009 Microchip Technology Inc. ® L security ICs, CAN ® ...
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... Maximum allowable current is a function of device maximum power dissipation (see Table 22-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the V and PGEDx pins, which are able to sink/source 12 mA. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 SS .................................................................................. -0.3V to +5.6V SS ...
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... PIC24HJ12GP201/202 40 40 Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +140 °C -40 — +125 ° INT – T )/θ Typ Max Unit Notes 45 — °C — °C — °C — °C — °C — °C/W 1 © 2009 Microchip Technology Inc. ...
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... This is the limit to which These parameters are characterized by similarity, but are not tested in manufacturing voltage must remain at Vss for a minimum of 200 µs to ensure POR. DD © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature (1) Min Typ Max 3 ...
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... OSC1 DD Preliminary (3) 3.3V 10 MIPS (3) 3.3V 16 MIPS (3) 3.3V 20 MIPS (3) 3.3V 30 MIPS 3.3V 40 MIPS . SS © 2009 Microchip Technology Inc. ...
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... Peripheral Module IDLE Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled These parameters are characterized, but are not tested in manufacturing. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 ) IDLE Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
Page 190
... Preliminary ) PD Conditions (3,4) Base Power-Down Current (3,5) Watchdog Timer Current: ΔI WDT -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Conditions 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 40 MIPS © 2009 Microchip Technology Inc. ...
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... Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for a list of 5V tolerant pins. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
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... DD core voltage DD Preliminary ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 2mA 3. 2mA 3. -2 -1 ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions 2.55 V © 2009 Microchip Technology Inc. ...
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... These parameters are ensured by design, but are not characterized or tested in manufacturing. TABLE 22-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristics No. C External Filter Capacitor EFC Value © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (3) (1) Min Typ ...
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... OSC2 output Min Typ Max — — 15 — — 50 — — 400 Preliminary ≤ +85°C for Industrial ≤ +125°C for Extended Units Conditions and HS modes when external clock is used to drive OSC1 pF EC mode C™ mode © 2009 Microchip Technology Inc. ...
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... Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: These parameters are characterized by similarity, but are tested in manufacturing These parameters are characterized by similarity, but are not tested in manufacturing. 6: Data for this parameter is preliminary. This parameter is characterized, but is not tested in manufacturing. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 ...
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... MHz ECPLL and XTPLL modes MHz Measured over 100 ms period ≤ +85°C for industrial A ≤ +125°C for Extended A Conditions ≤ +85° 3.0-3. ≤ +125° 3.0-3. Conditions ≤ +85° 3.0-3. ≤ +125° 3.0-3. 1). See Section 19.4 “Watchdog © 2009 Microchip Technology Inc. ...
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... T CNx High or Low Time (input) RBP Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: These parameters are characterized, but are not tested in manufacturing. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
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... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 22-1 for load conditions. DS70282D-page 196 SY10 SY20 SY13 Preliminary © 2009 Microchip Technology Inc. SY13 ...
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... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: These parameters are characterized, but are not tested in manufacturing. © 2009 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
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... Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz 1.5 T — CY © 2009 Microchip Technology Inc. ...