PIC24HJ64GP510A-E/PF Microchip Technology, PIC24HJ64GP510A-E/PF Datasheet - Page 137

16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY

PIC24HJ64GP510A-E/PF

Manufacturer Part Number
PIC24HJ64GP510A-E/PF
Description
16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP510A-E/PF

Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24HJ64GP510A-E/PF
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
PIC24HJ64GP510A-E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
10.0
The PIC24HJXXXGPX06A/X08A/X10A devices pro-
vide the ability to manage power consumption by selec-
tively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and a
reduction in the number of circuits being clocked con-
stitutes
PIC24HJXXXGPX06A/X08A/X10A devices can man-
age power consumption in four different ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
10.1
PIC24HJXXXGPX06A/X08A/X10A devices allow a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or high-preci-
sion oscillators by simply changing the NOSC bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limitations to the pro-
cess, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
EXAMPLE 10-1:
 2009 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended
reference source. To complement the
information in this data sheet, refer to
Section 9. “Watchdog Timer and
Power-Saving Modes” (DS70236) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
lower
PWRSAV INSTRUCTION SYNTAX
to
be
consumed
; Put the device into SLEEP mode
; Put the device into IDLE mode
PIC24HJXXXGPX06A/X08A/X10A
a
comprehensive
power.
Preliminary
10.2
PIC24HJXXXGPX06A/X08A/X10A devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
mode stops clock operation and halts all code execu-
tion. Idle mode halts the CPU and code execution, but
allows peripheral modules to continue operation. The
assembly syntax of the PWRSAV instruction is shown in
Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
10.2.1
Sleep mode has these features:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may continue
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled.
• Any form of device Reset.
• A WDT time-out.
On wake-up from Sleep, the processor restarts with the
same clock source that was active when Sleep mode
was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current.
during Sleep mode since the system clock source
is disabled.
the WDT is enabled.
prior to entering Sleep mode.
to operate in Sleep mode. This includes items such
as the input change notification on the I/O ports, or
peripherals that use an external clock input. Any
peripheral that requires the system clock source for
its operation is disabled in Sleep mode.
Note:
Instruction-Based Power-Saving
Modes
SLEEP MODE
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
DS70592B-page 137

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