PIC24HJ64GP510A-E/PF Microchip Technology, PIC24HJ64GP510A-E/PF Datasheet - Page 16

16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY

PIC24HJ64GP510A-E/PF

Manufacturer Part Number
PIC24HJ64GP510A-E/PF
Description
16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP510A-E/PF

Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
TABLE 3-3:
TABLE 3-4:
DS70152H-page 16
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C FPOR
0xF8000E
0xF80010
0xF80012
0xF80014
0xF80016
Legend: — = unimplemented bit, read as ‘0’.
Note 1:
0xF80000 FBS
0xF80002 Reserved
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
Legend: — = unimplemented bit, read as ‘0’.
Note 1:
Address
Address
2:
2:
3:
These reserved bits read as ‘1’ and must be programmed as ‘1’.
The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB ICD 2 and REAL
ICE in-circuit emulator clear this bit by default when connecting to a device.
These bits are reserved (read as ‘1’) and must be programmed as ‘1’.
This bit reads the current programmed value.
The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB
ICE™ in-circuit emulator clear this bit by default when connecting to a device.
FBS
Reserved
FGS
FOSCSEL
FOSC
FWDT
FICD
FUID0
FUID1
FUID2
FUID3
Name
Name
dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 DEVICE CONFIGURATION
REGISTER MAP
dsPIC33FJ12GP201/202 AND PIC24HJ12GP201/201 DEVICE CONFIGURATION
REGISTER MAP
FWDTEN
IESO
Bit 7
FWDTEN
FCKSM<1:0>
IESO
Bit 7
Reserved
FCKSM<1:0>
Reserved
WINDIS
Bit 6
WINDIS
(1)
(1)
Bit 6
JTAGEN
IOL1WAY
JTAGEN
IOL1WAY
Bit 5
Bit 5
(3)
(2)
WDTPRE
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
Bit 4
ALTI2C
Bit 4
Reserved
Reserved
(1)
Bit 3
Bit 3
(2)
BSS<2:0>
OSCIOFNC
WDTPOST<3:0>
BSS<2:0>
OSCIOFNC POSCMD<1:0>
© 2010 Microchip Technology Inc.
WDTPOST<3:0>
Bit 2
Bit 2
GSS<1:0>
GSS<1:0>
FNOSC<2:0>
FPWRT<2:0>
FNOSC<2:0>
FPWRT<2:0>
®
ICD 2 and REAL
POSCMD<1:0>
Bit 1
Bit 1
ICS<1:0>
ICS<1:0>
GWRP
GWRP
BWRP
BWRP
Bit 0
Bit 0

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