PIC24HJ64GP510A-E/PF Microchip Technology, PIC24HJ64GP510A-E/PF Datasheet - Page 33

16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY

PIC24HJ64GP510A-E/PF

Manufacturer Part Number
PIC24HJ64GP510A-E/PF
Description
16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP510A-E/PF

Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
5.2
As illustrated in
Verify mode requires three steps:
1.
2.
3.
The programming voltage applied to MCLR is V
which is essentially V
PIC24H devices. There is no minimum time require-
ment for holding at V
of at least P18 must elapse before presenting the key
sequence on PGDx.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more
hexadecimal). The device will enter Program/Verify
mode only if the sequence is valid. The Most Significant
bit of the most significant nibble must be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time P19 and P7 must elapse before presenting
data on PGDx. Signals appearing on PGDx before P7
has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in the
high-impedance state.
5.3
After entering into ICSP mode, the CPU is Idle.
Execution of the CPU is governed by an internal state
machine. A 4-bit control code is clocked in using PGCx
and PGDx and this control code is used to command the
CPU (see
The SIX control code is used to send instructions to the
CPU for execution and the REGOUT control code is
used to read data out of the device via the VISI register.
TABLE 5-1:
© 2010 Microchip Technology Inc.
Control Code
0000b
0001b
0010b-1111b
Note 1: The MCLR capacitor value can vary the
MCLR is briefly driven high then low (P21)
A 32-bit key sequence is clocked into PGDx.
MCLR is then driven high within a specified
period of time and held.
4-Bit
easily
Entering ICSP Mode
ICSP Operation
Table
high time required for entering ICSP
mode.
5-1).
SIX
REGOUT
N/A
Mnemonic
remembered
Figure
CPU CONTROL CODES IN
ICSP™ MODE
IH
. After V
DD
5-5, entering ICSP Program/
in the case of dsPIC33F/
Shift in 24-bit instruction
and execute.
register.
Reserved.
Shift out the VISI
IH
is removed, an interval
as
Description
0x4D434851
IH
must be
(1)
.
IH
in
,
5.3.1
The SIX control code allows execution of dsPIC33F/
PIC24H Programming Specification assembly instruc-
tions. When the SIX code is received, the CPU is sus-
pended for 24 clock cycles, as the instruction is then
clocked into the internal buffer. Once the instruction is
shifted in, the state machine allows it to be executed over
the next four clock cycles. While the received instruction
is executed, the state machine simultaneously shifts in
the next 4-bit command (see
5.3.2
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register out of the device
over the PGDx pin. After the REGOUT control code is
received, the CPU is held Idle for eight cycles. After these
eight cycles, an additional 16 cycles are required to clock
the data out (see
The REGOUT code is unique because the PGDx pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGDx pin becomes an output as the VISI register is
shifted out.
Note:
Note 1: Coming out of the ICSP entry sequence,
2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
SIX SERIAL INSTRUCTION
EXECUTION
REGOUT SERIAL INSTRUCTION
EXECUTION
The device will latch input PGDx data on
the rising edge of PGCx and will output
data on the PGDx line on the rising edge
of PGCx. For all data transmissions, the
Least Significant bit (LSb) is transmitted
first.
the first 4-bit control code is always
forced to SIX and a forced NOP instruction
is executed by the CPU. Five additional
PGCx clocks are needed on start-up,
thereby resulting in a 9-bit SIX command
instead of the normal 4-bit SIX command.
After the forced SIX is clocked in, ICSP
operation resumes as normal (the next
24 clock cycles load the first instruction
word to the CPU). See
details.
instructions must be followed by a NOP
instruction.
Figure
5-4).
Figure
5-3).
DS70152H-page 33
Figure 5-2
for

Related parts for PIC24HJ64GP510A-E/PF