SST25VF512A-33-4I-QAE Microchip Technology, SST25VF512A-33-4I-QAE Datasheet
SST25VF512A-33-4I-QAE
Specifications of SST25VF512A-33-4I-QAE
Related parts for SST25VF512A-33-4I-QAE
SST25VF512A-33-4I-QAE Summary of contents
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... Erase or Program operation is less than alternative flash memory technologies. The SST25VF512A device operates with a single 2.7-3.6V power supply. The SST25VF512A device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 1 for the pin assignments. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. ...
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... Data Sheet UNCTIONAL LOCK IAGRAM Address Buffers and Latches CE# ©2006 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD# 2 512 Kbit SPI Serial Flash SST25VF512A SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1264 B1.0 S71264-02-000 1/06 ...
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... Kbit SPI Serial Flash SST25VF512A PIN DESCRIPTION CE Top View WP 1264 08-soic P1.0 8- SOIC LEAD FIGURE SSIGNMENTS TABLE ESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input ...
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... BFH Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). 48H The SST25VF512A supports both Mode 0 (0,0) and Mode T2.0 1264 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... W OLD ONDITION Write Protection The SST25VF512A provides software Write protection. The Write Protect pin (WP#) enables or disables the lock- down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status regis- ter ...
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... Chip-Erase instruction completion ©2006 Silicon Storage Technology, Inc. 512 Kbit SPI Serial Flash Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Default at Power-up 6 SST25VF512A Read/Write R/W 1 R/W ...
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... Kbit SPI Serial Flash SST25VF512A Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table software pro- tected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0 ...
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... Data Sheet Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25VF512A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...
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... Kbit SPI Serial Flash SST25VF512A Read (20 MHz) The Read instruction outputs the data starting from the specified address location. The data output stream is con- tinuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached ...
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... Mbit density, once the data from address location 07FFFFH has been read, the next output will be from address location 000000H ADD. ADD. ADD. X MSB MSB EQUENCE 10 512 Kbit SPI Serial Flash SST25VF512A N+1 N+2 N+3 N OUT OUT OUT OUT OUT 1264 F05.0 ...
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... Kbit SPI Serial Flash SST25VF512A Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored. ...
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... Data Byte 1 A[7: Write Disable (WRDI) Instruction to terminate AAI Operation (AAI ROGRAM EQUENCE 12 512 Kbit SPI Serial Flash SST25VF512A for the completion of each inter Data Byte 2 05 Read Status Register (RDSR) Instruction to verify end of AAI Operation D OUT 1264 F07.0 S71264-02-000 1/06 ...
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... Kbit SPI Serial Flash SST25VF512A Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the any command sequence ...
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... Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 11 for the RDSR instruction sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB (RDSR) S EQUENCE 14 512 Kbit SPI Serial Flash SST25VF512A Status 1264 F11.0 Register Out S71264-02-000 CE 1/06 ...
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... Kbit SPI Serial Flash SST25VF512A Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE# must be driven high before the WREN instruction is executed. FIGURE 12: W ...
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... WRSR instruction is executed. See Figure 14 for EWSR and WRSR instruction sequences MODE 3 MODE 0 01 MSB HIGH IMPEDANCE -R (EWSR EGISTER AND RITE TATUS 16 512 Kbit SPI Serial Flash SST25VF512A ) prior to the low-to-high transi- IH STATUS REGISTER MSB 1264 F14.0 -R (WRSR) S EGISTER EQUENCE S71264-02-000 1/06 ...
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... Kbit SPI Serial Flash SST25VF512A Read-ID The Read-ID instruction identifies the device as SST25VF512A and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A the Read-ID instruction, the manufacturer’ located in CE# MODE MODE 0 ...
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... Max Units Test Conditions 10 mA CE#=0 CE#=V 15 µA CE#=V 1 µ µA V OUT OWER UP IMINGS 18 512 Kbit SPI Serial Flash SST25VF512A EST = /0.9 V @20 MHz, SO=open =GND Max =GND Max Min DD =V Max DD =100 µ Min DD DD =-100 µ Min ...
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... Kbit SPI Serial Flash SST25VF512A TABLE 9: C APACITANCE (T = 25°C, f=1 Mhz, other pins open) A Parameter Description 1 C Output Pin Capacitance OUT 1 C Input Capacitance IN 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ...
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... CE# T SCKH SCK T CLZ SO SI FIGURE 17 ERIAL UTPUT IMING ©2006 Silicon Storage Technology, Inc. T SCKF T SCKR D IAGRAM T SCKL T OH MSB IAGRAM 20 512 Kbit SPI Serial Flash SST25VF512A T CPH T T CEH CHS LSB HIGH-Z 1264 F16.0 T CHZ LSB 1264 F17.0 S71264-02-000 1/06 ...
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... Kbit SPI Serial Flash SST25VF512A CE# SCK SO SI HOLD# FIGURE 18 OLD IMING IAGRAM Max DD Chip selection is not allowed. All commands are rejected by the device. V Min DD FIGURE 19 OWER UP IMING ©2006 Silicon Storage Technology, Inc HHH HLS T HLH PU-READ T PU-WRITE D IAGRAM 21 Data Sheet ...
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... DD ILT DD ) and V (0.3V ). Input rise and fall times (10 EFERENCE AVEFORMS TO TESTER TO DUT 1264 F21.0 22 512 Kbit SPI Serial Flash SST25VF512A V HT OUTPUT V LT 1264 F20.0 ) for a logic “0”. Measurement reference points ↔ 90%) are <5 ns. Note Test HT HIGH Test LT LOW V ...
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... XX Valid combinations for SST25VF512A SST25VF512A-33-4C-SAE SST25VF512A-33-4C-QAE SST25VF512A-33-4I-SAE SST25VF512A-33-4I-QAE SST25VF512A-33-4E-SAE SST25VF512A-33-4E-QAE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc. ...
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... Silicon Storage Technology, Inc. SIDE VIEW 7˚ 4 places 0.51 0.33 1.27 BSC 0.25 0.10 1.75 0.25 1.35 0.19 C (SOIC) 150 IRCUIT MIL BODY WIDTH 24 512 Kbit SPI Serial Flash SST25VF512A END VIEW 45˚ 7˚ 4 places 0˚ 8˚ 1.27 0.40 08-soic-5x6-SA-8 1mm (4 S71264-02-000 1/06 ...
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... Kbit SPI Serial Flash SST25VF512A TOP VIEW Pin #1 Corner 6.00 ± 0.10 Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. The external paddle is electrically connected to the die back-side and possibly to certain V This paddle can be soldered to the PC board ...