SC28C94A1N NXP Semiconductors, SC28C94A1N Datasheet
SC28C94A1N
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SC28C94A1N Summary of contents
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SC28C94 Quad universal asynchronous receiver/transmitter (QUART) Product data sheet Supersedes data of 1998 Aug 19 INTEGRATED CIRCUITS 2006 Aug 09 ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) DESCRIPTION The 28C94 quad universal asynchronous receiver/transmitter (QUART) combines four enhanced Philips Semiconductors industry-standard UARTs with an innovative interrupt scheme that can vastly minimize host processor overhead implemented using Philips Semiconductors’ ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) PIN CONFIGURATIONS 8 RXDB I/O3B RXDA TXDA ABSOLUTE MAXIMUM ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) BLOCK DIAGRAM 8 BUS BUFFER D0–D7 OPERATION CONTROL RDN WRN ADDRESS DECODE CEN 6 A0–A5 R/W CONTROL RESET DACKN TIMING 2 CRYSTAL X1/CLK OSCILLATOR POWER UP-DOWN X2 LOGIC BAUD RATE GENERATOR DUART CD ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) PIN DESCRIPTION MNEMONIC TYPE CEN I Chip Select: Active low input that, in conjunction with RDN or WRN, indicates that the host MPU is trying to access a QUART register. CEN must be ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) 1 Table 1. QUART Registers A5:0 READ (RDN = Low) 000000 Mode Register a (MR0a, MR1a, MR2a) 000001 Status Register a (SRa) 000010 Reserved 000011 Receive Holding Register a (RxFIFOa) 000100 Input Port ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) FUNCTIONAL BLOCKS The QUART is composed of four Philips Semiconductors industry–standard UARTs, each having a separate transmit and receive channel. The Basic UART cells in the QUART are configured with 8-byte Receive FIFOs ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) set each time the counter/timer transitions from (High to low) This continues regardless of issuance of the stop counter command. ISR[3] is reset by the stop counter command. NOTE: Reading ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) or break condition, and presents the assembled character to the CPU via the receiver FIFO. The receiver operates in two modes: the 1X and 16X. The 16X mode is the more robust of ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) WAKE-UP MODE (MULTI-DROP OR 9-BIT) In addition to the normal transmitter and receiver operation described above, the QUART incorporates a special mode which provides automatic “wake up” receiver through address frame ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Functional Description of the Interrupt Arbitration For the purpose of this description, a ‘source’ is any one of the 18 QUART circuits that may generate an interrupt. The QUART contains eighteen sources which ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Arbitration - Aftermath At the end of the arbitration, i.e., the falling edge of EVAL, the winning interrupt source is driving its Channel number, number of bytes (if applicable) and interrupt type onto ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Vectored Interrupts The QUART responds to an Interrupt Acknowledge (IACK) initiated by the host by providing an Interrupt Acknowledge Vector on D7:0. The interrupt acknowledge cycle is terminated with a DACKN pulse. The ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Table 4. Register Bit Formats, Duart ab. [duplicated for Duart cd] (continued) Bit 7 Bit 6 Bit 5 SR (Status Register) Rec’d. Break Framing Error Parity Error ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Mode Registers 0, 1 and 2 The addressing of the Mode Registers is controlled by the MR Register pointer. On any access to the Mode Registers this pointer is always incremented. Upon reaching ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) The user must exercise care when switching into and out of the various modes. The selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) 1001 Negate RTSN. Causes the RTSN output to be negated (High). 1010 Set Timeout Mode On. The register in this channel will restart the C/T as each receive character is transferred from the ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) SR – Channel Status Register SR[7] – Received Break This bit indicates that an all zero character of the programmed length has been received without a stop bit. Only a single FIFO position ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) IPCR – Input Port Change Register IPCR[7:4] – I/O1b, I/O0b, I/O1a, I/O0a Change-of-State Detectors These bits are set when a change of state, as defined in the Input Port section of this data ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) In the counter mode, the C/T counts down the number of pulses loaded in CTUR and CTLR by the CPU. Counting begins upon receipt of a start counter command. Upon reaching the terminal ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Table 8. Register Bit Formats, I/O Section Bit 7 Bit 6 Bit 5 IPCR (Input Port Change Register ab) The lower four bits replicate the lower four bits of the IPR. The upper ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) I/O Port Control Channel B (IOPCRB) IOPCRb[7:6] IOPCR[xx] Pin Control Bits I/O3B 00 = input IPR(7), TxC output OPRab( output TxC 16x 11 = output TxC 1x I/O ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Registers of the Interrupt System The CIR, and “Global” registers are updated with the IACKN signal or from the “Update CIR” command at hex address 2A. These registers are not updated when IRQN ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) DC ELECTRICAL CHARACTERISTICS 10 – unless otherwise specified SYMBOL SYMBOL PARAMETER PARAMETER V Input low voltage Input high voltage ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS 10 – unless otherwise specified SYMBOL SYMBOL FIGURE FIGURE Reset timing t 10 Reset pulse width RES I/O Port ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS – unless otherwise specified NO. FIGURE FIGURE 1 4 A[5:0] Setup time to RDN WRN ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS 10 – +85 C, unless otherwise specified NO. NO FIGURE FIGURE 1 5 Setup: A[5:0] valid to CEN Low 2 5 ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) AC ELECTRICAL CHARACTERISTICS – +85 C, unless otherwise specified NO. NO FIGURE FIGURE CHARACTERISTIC CHARACTERISTIC 1 6 D[7:0] Valid after IACKN ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) HOLD EN BYTE COUNTER TRANSMITTER OFFSET CORRECTION LOGIC IACK BYTE COUNT UPDCIR READ GIBC READ CIR READ CICR D7 D6 INTRAN–INTRDN, I/O0a–I/O3d D0–D7, TxDa–TxDh, I/O0a–I/O3d 2006 Aug 09 INTBUSN7:0 INVERTING LATCHES INTERRUPT TYPE ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) RESET RDN t PS I/O as Input I/O PINS MUST BE STABLE FOR NON-CHANGING BUS DATA DURING THE READ. CEN WRN I/O as Output NOTE: I/O PIN DATA IS NOT LATCHED WRN 1 ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) t CLK t CTC X1/CLK CTCLK RxC TxC 24pF FOR and C2 should be chosen according to the crystal manufacturer’s specification. C1 ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) RxC (1X INPUT) RxD TxD D1 TRANS- MITTER ENABLED TxRDY (SR2) MR0(5: WRN CTSN (I/O0) 2 RTSN (I/O1) CR[7:4] = 1010 NOTES: 1. TIMING SHOWN FOR MR2[4] = ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) RxD D1 D2 RECEIVER ENABLED RxRDY (SR0) D2 FFULL (SR1) RxRDY/ FFULL ISR(1) RDN OVERRUN (SR4) 1 RTS I/O1 I/ (CR[7:4] = 1010) NOTES; 1. TIMING SHOWN ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) INTERRUPT NOTES The following is a brief description of the new QUART “Bidding” interrupt system, interrupt vector and the use of the Global registers. The new features of the QUARTs have been developed ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) through the most significant 6 bits. The result of this is that the channel value does not ’bid’. However the logic is such that other parts of the bid being equal the condition ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) addressed register. The generation of DACKN begins with the start of a bus cycle (Read, Write or Interrupt Acknowledge) and then requires two edges of the X1 clock plus typically 70ns for its ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) PLCC52: plastic leaded chip carrier; 52 leads 2006 Aug 09 37 Product data sheet SC28C94 SOT238-2 ...
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... Deleted (old) Figure 1 on page 2 Ordering information: – changed DWG # for PLCC52 from SOT238–3 to SOT238–2 – deleted 48-pin DIP package (SC28C94A1N; SOT240–1) (discontinued) Removed pin configuration for 48-pin DIP from (new) Figure 1, “Pin configuration” ABSOLUTE MAXIMUM RATINGS table on page 3: removed P Deleted SOT240– ...
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Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) Legal Information Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document ...