USB3320C-EZK Standard Microsystems (SMSC), USB3320C-EZK Datasheet
USB3320C-EZK
Specifications of USB3320C-EZK
Available stocks
Related parts for USB3320C-EZK
USB3320C-EZK Summary of contents
Page 1
PRODUCT FEATURES Integrated ESD protection circuits — ±15kV IEC Air Discharge without external devices Over-Voltage Protection circuit (OVP) protects the VBUS pin from continuous DC voltages up to 30V Integrated USB Switch — No degradation of Hi-Speed electrical ...
Page 2
... USB3320C-EZK for 32 pin, QFN Lead-Free RoHS Compliant Package USB3320C-EZK-TR for 32 pin, QFN Lead-Free RoHS Compliant Package (tape and reel) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
Page 3
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 0.1 Reference Documents Universal Serial Bus Specification, Revision 2.0, April 27, 2000 On-The-Go Supplement to the USB 2.0 Specification, Revision 2.0, May 8, 2009 USB Specification Revision 2.0 "Pull-up/pull-down resistors" ...
Page 4
Table of Contents 0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.1.1 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
List of Figures Figure 1.1 USB3320 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet List of Tables Table 2.1 USB3320 Pin Description . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
Chapter 1 General Description The SMSC USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution and is an excellent match for a wide variety of products. Both commercial and industrial temperature applications are supported. ...
Page 9
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet The USB3320 includes an integrated 3.3V Low Drop Out (LDO) regulator that may optionally be used to generate 3.3V from power applied at the VBAT pin. The voltage on the ...
Page 10
Chapter 2 USB3320 Pin Locations and Definitions 2.1 USB3320 Pin Locations and Descriptions 2.1.1 Package Diagram with Pin Locations The illustration below is viewed from the top of the package. Figure 2.1 USB3320 Pin Locations - Top View 2.1.2 Pin ...
Page 11
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 2.1 USB3320 Pin Description (continued) PIN NAME 2 NXT 3 DATA[0] 4 DATA[1] 5 DATA[2] 6 DATA[3] 7 DATA[4] 8 REFSEL[0] 9 DATA[5] 10 DATA[6] 11 REFSEL[1] 12 N/C ...
Page 12
Table 2.1 USB3320 Pin Description (continued) PIN NAME 17 CPEN VDD33 21 VBAT 22 VBUS RBIAS REFCLK 27 RESETB 28 VDD18 Revision 1.0 (07-14-09) Highly Integrated Full Featured Hi-Speed ...
Page 13
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 2.1 USB3320 Pin Description (continued) PIN NAME 29 STP 30 VDD18 31 DIR 32 VDDIO FLAG GND SMSC USB3320 DIRECTION/ ACTIVE TYPE LEVEL Input, High The Link asserts STP ...
Page 14
Chapter 3 Limiting Values 3.1 Absolute Maximum Ratings PARAMETER SYMBOL VBUS, VBAT, ID, CPEN, V MAX_5V DP, DM, SPK_L, and SPK_R voltage to GND Maximum VDD18 voltage V MAX_18V to Ground Maximum VDDIO voltage V MAX_IOV to Ground Maximum VDDIO ...
Page 15
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 4 Electrical Characteristics The following conditions are assumed unless otherwise specified 3.1 to 5.5V; V VBAT The current for 3.3V circuits is sourced at the VBAT pin, ...
Page 16
Clock Specifications PARAMETER SYMBOL Suspend Recovery Time T Note 4.3 PHY Preparation Time T CLKOUT Duty Cycle DC REFCLK Duty Cycle DC REFCLK Frequency Accuracy F Note 4.3 The Suspend Recovery Time is measured from the start of the ...
Page 17
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 4.4 Digital IO Pins Table 4.4 Digital IO Characteristics: RESETB, CLKOUT, STP, DIR, NXT, DATA[7:0] & REFCLK Pins PARAMETER SYMBOL Low-Level Input Voltage V IL High-Level Input Voltage V IH ...
Page 18
Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER SYMBOL High Level Output Voltage V FSOH Termination Driver Output Impedance for Z HSDRV HS and FS Input Impedance Z INP Pull-up Resistor Impedance R PU Pull-up Resistor Impedance R ...
Page 19
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER SYMBOL Port Capacitance Transceiver Input C IN Capacitance Note 4.5 The resistor value follows the 27% Resistor ECN published by ...
Page 20
OTG Electrical Characteristics PARAMETER SYMBOL SessEnd trip point V SessEnd SessVld trip point V SessVld VbusVld trip point V VbusVld A-Device Impedance R IdGnd ID Float trip point V IdFloat VBUS Pull-Up R VPU VBUS Pull-down R VPD VBUS ...
Page 21
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 4.9 Regulator Output Voltages and Capacitor Requirement Table 4.9 Regulator Output Voltages and Capacitor Requirement PARAMETER SYMBOL Regulator Output Voltage V DD33 Regulator Output Voltage V DD33 Regulator Output Voltage ...
Page 22
Piezoelectric Resonator for Internal Oscillator The internal oscillator may be used with an external quartz crystal or ceramic resonator as described in Section 5.4.1.2. See ceramic resonator part numbers for commercial temperature applications. At this time, the ceramic resonator ...
Page 23
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 5 Architecture Overview The USB3320 consists of the blocks shown in the diagram below. All pull-up resistors shown in this diagram are connected internally to the VDD33 pin. CPEN ...
Page 24
HS transmitter amplitude. The Boost bits in the HS TX Boost register may be configured to adjust the HS transmitter amplitude at the DP and DM pins. 5.2.2 Termination ...
Page 25
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 5.1 DP/DM Termination vs. Signaling Mode (continued) SIGNALING MODE Host LS Resume Host Test J/Test_K Peripheral Settings Peripheral Chirp Peripheral HS Peripheral FS Peripheral HS/FS Suspend Peripheral HS/FS Resume ...
Page 26
Bias Generator This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the analog circuits. This block requires an external 8.06KΩ, 1% tolerance, reference resistor connected from RBIAS to ground. ...
Page 27
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet ULPI Clk Out Link Reference Clk In Figure 5.2 Configuring the USB332X for ULPI Input Clock Mode (60 MHz) 5.4.1.2 ULPI Output Clock When using ULPI Output Clock Mode, the ...
Page 28
ULPI Clk In Link Resonator - or - Crystal and Caps After the PLL has locked to the correct frequency, the USB3320 generates the 60MHz ULPI clock on the CLKOUT pin, and de-asserts DIR to indicate that the PLL is ...
Page 29
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 5.4.3 REFCLK Jitter The USB3320 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of less than 1nS over ...
Page 30
VBUS To USB Con. Figure 5.6 Powering the USB3320 from a Battery The USB3320 can be powered from an external 3.3V supply as shown below in using the external supply, both the VBAT and VDD33 pins are connected together. ...
Page 31
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet For peripheral only or host only operation, the VBAT supply shown below in connected to the VBUS pin of the USB connector for bus powered applications. In this configuration, external ...
Page 32
Table 5.3 Operating Mode vs. Power Supply Configuration VDD33 VDD18 Note: Anytime VBAT is powered per Note 5.2 VDDIO must be powered to tri-state the ULPI interface in ...
Page 33
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet T0 SUPPLIES STABLE REFCLK RESETB DATA[7:0] PHY Tri-States DIR PHY Tri-States STP 5.6 USB On-The-Go (OTG) The USB3320 provides full support for USB OTG protocol. OTG allows the USB3320 to ...
Page 34
VDD33 ID To USB Con Figure 5.10 USB3320 ID Resistor Detection Circuitry 5.6.1.1 USB OTG Operation The USB3320 can detect ID grounded and ID floating to determine cable has been inserted. ...
Page 35
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Table 5.4 Valid Values of ID Resistance to Ground ID RESISTANCE TO GROUND Ground 75Ω +/-1% 102kΩ +/-1% 200kΩ+/-1% 440kΩ +/-1% Floating Note: IdPullUp = 0 The Rid resistance can ...
Page 36
Note: The IdGnd switch has been provided to ground the ID pin for future applications. 5.6.2 VBUS Monitor and Pulsing The USB3320 includes all of the VBUS comparators required for OTG. The VBUSVld, SessVld, and SessEnd comparators shown in are ...
Page 37
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 5.6.2.2 SessVld Comparator The SessVld comparator is used when the transceiver is configured as both an A and B device. When configured device, the SessVld is used ...
Page 38
VBUS Pulsing with Pull-up and Pull-down Resistors In addition to the internal VBUS comparators, the USB3320 also includes the integrated VBUS pull-up and pull-down resistors used for VBUS Pulsing during OTG Session Request Protocol. To discharge the VBUS voltage ...
Page 39
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet For example, protecting a peripheral or device only application to 15V would require a 10kΩ R resistor with a power rating of 0.01W. To protect an OTG product to 15V ...
Page 40
RESETB 0 1 Note: ChargerPullupEnableDP and ChargerPullupEnableDM are enabled in the Management register. 5.9 USB Audio Support Note: The USB3320 supports “USB Digital Audio” through the USB protocol in ULPI and USB Serial modes described in The USB3320 provides two ...
Page 41
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 5.10 Reference Frequency Selection The USB3320 is configured for the desired reference frequency by the REFSEL[2], REFSEL[1] and REFSEL[0] pins pin is connected to VDDIO, the value of ...
Page 42
Chapter 6 ULPI Operation 6.1 Overview The USB3320 uses the industry standard ULPI digital interface to facilitate communication between the USB Transceiver (PHY) and Link (device controller). The ULPI interface is designed to reduce the number of pins required to ...
Page 43
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet low latency PHY allows a Link to use a wrapper around a UTMI Link and still make the required USB turn-around timing given in the USB 2.0 specification. RxEndDelay maximum ...
Page 44
Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor transceiver drive the data bus for one clock cycle. During the “turn–around“cycle, the state of DATA[7:0] is unknown and the transceiver will not read the data bus. ...
Page 45
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet CMD COMMAND NAME BITS[7:6] Idle 00b Transmit 01b Register Write 10b Register Read 11b 6.2.1 ULPI Register Write A ULPI register write operation is given in DATA[7:6] = 10b is ...
Page 46
At T4, the transceiver will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the ...
Page 47
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.2.2 ULPI Register Read A ULPI register read operation is given in = 11h for a register read. DATA[5:0] of the ULPI TXD command bye contain the register address. T0 ...
Page 48
T0 T1 CLK DATA[7:0] Idle extended reg read DIR STP NXT Figure 6.6 ULPI Extended Register Read in Synchronous Mode 6.2.3 ULPI RXCMD The ULPI Link needs information which was provided by the following pins in a UTMI implementation: linestate[1:0], ...
Page 49
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet DATA[7:0] NAME DESCRIPTION AND VALUE [1:0] Linestate UTMI Linestate Signals [3:2] Encoded ENCODED VBUS VOLTAGE STATES VBUS State VALUE [5:4] Rx Event ENCODED UTMI EVENT SIGNALS ...
Page 50
Several important functions for a device and host are designed into the transmitter blocks. The USB3320 transmitter will transmit a 32-bit long high speed sync before every high speed packet. In full and low speed modes a 8-bit sync is ...
Page 51
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.2.4.5 No SYNC and EOP Generation (OpMode = 11) UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in Hi-Speed operation. This is an option to the ...
Page 52
CLK Turn DATA[7:0] Idle around DIR STP NXT Figure 6.8 ULPI Receive in Synchronous Mode In Figure 6.8 the transceiver asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the ...
Page 53
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet on the DP and DM pins to avoid false linestate indications that could result if the pins were allowed to float. 6.3.1 Entering Low Power/Suspend Mode To enter Low Power ...
Page 54
Note 6.2 LineState: These signals reflect the current state of the Full-Speed single ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). ...
Page 55
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.3.3.1 Start up Protection Upon start-up, when the transceiver de-asserts DIR, the Link must be ready to receive commands and drive Idle on the data bus. If the Link is ...
Page 56
Link can disable the pull-up resistor on STP. When RESETB is low the Interface Protect Circuit will be disabled. 6.4 Full Speed/Low Speed Serial Modes The USB3320 includes two serial modes to support legacy Links which use either the ...
Page 57
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.4.0.2 6Pin FS/LS Serial Mode Six pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.6 Pin Definitions in 6 Pin Serial Mode CONNECTED ...
Page 58
USB UART Mode The USB3320 can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Control register. Then the Link can set the CarkitMode bit in the and RxdEn bits must be written ...
Page 59
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 6.5.2 USB Audio Mode When the USB3320 is powered in Synchronous Mode, the Audio switches can be enabled by asserting the SpkLeftEn, or SpkRightEn bits in the the USB3320 will ...
Page 60
The ULPI interface is redefined as shown in Table 6.10 Pin Definitions in Headset Audio Mode CONNECTED SIGNAL TO SessVld DATA[0] VbusVld DATA[1] IdGndDrv DATA[2] DATA[3] IdGround DATA[4] IdFloat DATA[5] IdPullup330 DATA[6] IdPullup DATA[7] Exiting Headset Audio Mode is the ...
Page 61
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 7 ULPI Register Map 7.1 ULPI Register Array The USB3320 Transceiver implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The complete USB3320 ULPI register ...
Page 62
REGISTER NAME Reserved Vendor Rid Conversion USB IO & Power Management Reserved Note 7.1 Dynamically updates to reflect current status of interrupt sources. 7.1.1 ULPI Register Set The following registers are used for the ULPI interface. 7.1.1.1 Vendor ID Low ...
Page 63
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME BIT ACCESS Product ID High 7:0 7.1.1.5 Function Control Address = 04-06h (read), 04h (write), 05h (set), 06h (clear) FIELD NAME BIT ACCESS XcvrSelect[1:0] 1:0 TermSelect 2 OpMode ...
Page 64
FIELD NAME BIT ACCESS ClockSuspendM 3 AutoResume 4 IndicatorComplement 5 IndicatorPassThru 6 InterfaceProtectDisable 7 7.1.1.7 OTG Control Address = 0A-0Ch (read), 0Ah (write), 0Bh (set), 0Ch (clear) FIELD NAME BIT ACCESS IdPullup 0 DpPulldown 1 DmPulldown 2 DischrgVbus 3 ChrgVbus ...
Page 65
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DrvVbusExternal 6 UseExternalVbus 7 Indicator 7.1.1.8 USB Interrupt Enable Rising Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear) FIELD NAME BIT ACCESS HostDisconnect Rise ...
Page 66
FIELD NAME BIT ACCESS Reserved 7:5 7.1.1.10 USB Interrupt Status Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources. FIELD NAME BIT ACCESS HostDisconnect 0 VbusValid 1 SessValid 2 SessEnd 3 IdGnd 4 ...
Page 67
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 7.1.1.12 Debug Address = 15h (read only) FIELD NAME BIT ACCESS Linestate0 0 Linestate1 1 Reserved 7:2 7.1.1.13 Scratch Register Address = 16-18h (read), 16h (write), 17h (set), 18h (clear) ...
Page 68
If using USB UART mode the UART data will appear at the SPK_L and SPK_R pins if the corresponding SpkLeftEn, SpkRightEn, or MicEn switches are enabled. If using USB Audio the TxdEn and RxdEn bits should not be set when ...
Page 69
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME BIT ACCESS RidValue 5:3 RidConversionDone 6 Reserved 7 7.1.2.4 Carkit Interrupt Latch Address = 21h (read only with auto-clear) FIELD NAME BIT ACCESS IdFloat Latch 0 (Note CarIntDet ...
Page 70
Vendor Register Access The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI immediate register read / write. 7.1.3 Boost Address = 31h (read / write) FIELD NAME BIT ...
Page 71
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet FIELD NAME BIT ACCESS RidConversionDone 3 (Note RidConversionStart 4 Reserved 5 RidIntEn 6 Reserved 7 Note 7.4 rd: Read Only with auto clear. 7.1.3.4 USB IO & Power Management Address ...
Page 72
FIELD NAME BIT ACCESS ChargerPullupEnDM 5 USB RegOutput 7:6 Revision 1.0 (07-14-09) Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver DEFAULT DESCRIPTION rd/w/s/c 0b Enables a Pull-up for USB Charger Detection when set on the DM pin. (The pull-up ...
Page 73
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Chapter 8 Application Notes 8.1 Application Diagram The USB3320 requires few external components as shown in the application diagrams. The USB 2.0 Specification restricts the voltage at the VBUS pin ...
Page 74
R must be installed to VBUS enable overvoltage protection of the VBUS pin. 3.1-5.5V Supply The capacitor C VBUS must be installed on this side VBUS C VBUS USB Receptacle VBUS DM DP SHIELD GND C DC_BLOCK ...
Page 75
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet R must be installed to VBUS enable overvoltage protection of the VBUS pin. 3.1-5.5V Supply The capacitor C VBUS must be installed on this side VBUS C ...
Page 76
VDDIO Supply R must be VBUS installed to enable overvoltage VBUS protection of the Switch VBUS pin VBUS 5V IN OUT 3.1-5.5V The capacitor C Supply VBUS must be installed on this side VBUS C ...
Page 77
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet 8.3.1 Human Body Model (HBM) Performance HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing, and is done without power applied ...
Page 78
Chapter 9 Package Outline, Tape & Reel Drawings, Package Marking The USB3320 is offered in a compact 32 pin lead-free QFN package. Figure 9.1 USB3320 32 Pin QFN Package Outline 0.9 mm Body (Lead-Free) Table 9.1 ...
Page 79
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Figure 9.2 QFN, 5x5 Taping Dimensions and Part Orientation SMSC USB3320 79 DATASHEET Revision 1.0 (07-14-09) ...
Page 80
Figure 9.3 Reel Dimensions for 12mm Carrier Tape Revision 1.0 (07-14-09) Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver 80 DATASHEET Datasheet SMSC USB3320 ...
Page 81
Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Datasheet Figure 9.4 Tape Length and Part Quantity Note: Standard reel size is 4000 pieces per reel. SMSC USB3320 Figure 9.5 Package Marking 81 DATASHEET Revision 1.0 (07-14-09) ...
Page 82
Chapter 10 Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY Rev. 1.0 (07-14-09) Initial Release Revision 1.0 (07-14-09) Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Table 10.1 Customer Revision History 82 DATASHEET Datasheet CORRECTION SMSC USB3320 ...