CY7C68000-56PVC Cypress Semiconductor Corp, CY7C68000-56PVC Datasheet
CY7C68000-56PVC
Specifications of CY7C68000-56PVC
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CY7C68000-56PVC Summary of contents
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... PLL_480 Fast Traffic Elasticity Digital Sync Buffer Rx Fast Digital Tx Figure 1-1. Block Diagram • 198 Champion Court • San Jose CY7C68000 UTMI CLK UTMI CLK UTMI Rx Ctl Digital Rx UTMI Rx Data 8/16 BIDI Option Also Tx UTMI Rx Data 8/16 Digital Tx UTMI Tx Ctl , CA 95134-1709 • ...
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... DPLUS/DMINUS Impedance Termination has CC The CY7C68000 does not require external resistors for USB data line impedance termination or an external pull up resistor on the DPLUS line. These resistors are incorporated into the part. They are factory trimmed to meet the requirements of USB 2.0. Incorporating these resistors also reduces the pin count on the part ...
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... The packages offered use either an 8-bit (60-MHz) or 16-bit (30-MHz) bus interface. TXReady 1 Suspend 2 Reset XTALOUT 5 XTALIN 6 AGND DPLUS 9 DMINUS 10 AGND 11 XcvrSelect 12 TermSelect 13 OpMode0 14 Figure 5-1. CY7C68000 56-pin QFN Pin Assignment Document #: 38-08016 Rev. *H 56-pin QFN CY7C68000 56-pin QFN CY7C68000 GND Reserved Reserved 35 D10 34 D11 D12 31 ...
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... Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment 5.1 CY7C68000 Pin Descriptions [1] Table 5-1. Pin Descriptions SSOP QFN Name Type 11 4 AVCC Power 15 8 AVCC Power 14 7 AGND Power 18 11 AGND Power 16 9 DPLUS I/O DMINUS I/O/Z Note: 1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure signals at power-up and in standby ...
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... HS termination 1: FS termination N/A Suspend. Places the CY7C68000 in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume opera- tions. While suspended, TermSelect must always mode to ensure that the 1.5 K ohm pull-up on DPLUS remains powered. ...
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... TX Holding Register on the rising edge of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of CLK, the CY7C68000 will load the data on the data bus into the TX Holding Register on the next rising edge of CLK. At that time, the SIE should immedi- ately present the data for the next transfer on the data bus Receive Data Valid ...
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... Connect to 3.3V power source Connect to 3.3V power source Connect to 3.3V power source. CC N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. CY7C68000 Description Page ...
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... Crystal Frequency).... 24 MHz ± 100 ppm OSC ................................................................... Parallel Resonant + 0.5V CC Conditions 0< V < OUT I = –4 mA OUT Except DPLUS/DMINUS/CLK DPLUS/DMINUS/CLK Output pins [2] Connected [2] Disconnected Normal operation OPMOD[1: Normal operation OPMOD[1: CY7C68000 Min. Typ. Max. Unit 3.0 3.3 3 5.25 V –0.5 0.8 V μA ±10 2 ...
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... Minimum hold time for Data (transmit direction) DH_MIN T Clock to Control out time for TXReady, RXValid, CCO RXActive and RXError T Clock to Data out time (Receive direction) CDO Document #: 38-08016 Rev. *H TCH_MIN TCSU_MIN TDH_MIN TDSU_MIN Figure 9-1. 60-MHz Interface Timing Constraints Description CY7C68000 TCCO TCDO Min. Typ. Max. Unit ...
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... Minimum set-up time for ValidH (transmit Direction) VSU_MIN T Minimum hold time for ValidH (Transmit direction) VH_MIN T Clock to ValidH out time (Receive direction) CVO Document #: 38-08016 Rev. *H TCH_MIN TCSU_MIN TDH_MIN TDSU_MIN TVH_MIN TVSU_MIN Description CY7C68000 TCDO TCCO TCVO Min. Typ. Max. Unit ...
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... Ordering Information Table 10-1. Ordering Information Ordering Code CY7C68000-56LFXC CY7C68000-56LFXCT CY7C68000-56PVC CY7C68000-56PVCT CY7C68000-56PVXC CY7C68000-56PVXCT CY3683 11.0 Package Diagrams The TX2 is available in two packages: • 56-pin SSOP • 56-pin QFN. Figure 11-1. 56-lead Shrunk Small Outline Package O56 Document #: 38-08016 Rev. *H ...
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... DMINUS traces. Do not allow the plane to be split under these traces. • If possible, do not place any vias on the DPLUS or DMINUS trace routing. • Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. CY7C68000 BOTTOM VIEW PIN #1 0.18[0.007] 0.28[0.011] CORNER ...
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... Nitrogen purge is recommended during reflow. 0.017” dia Solder Mask Cu Fill Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane CY7C68000 Page ...
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... Document History Page Document Title: CY7C68000 TX2™ USB 2.0 UTMI Transceiver Document Number: 38-08016 REV. ECN NO. Issue Date ** 112019 03/01/02 *A 113885 07/01/02 *B 118521 11/18/02 *C 124507 02/21/03 *D 126665 07/03/03 *E 285634 SEE ECN *F 301832 SEE ECN *G 375694 SEE ECN *H 448451 SEE ECN Document #: 38-08016 Rev ...