ISP1301BS,157 NXP Semiconductors, ISP1301BS,157 Datasheet
ISP1301BS,157
Specifications of ISP1301BS,157
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ISP1301BS,157 Summary of contents
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ISP1301 USB On-The-Go transceiver Rev. 05 — 2 September 2009 1. General description The ISP1301 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to ...
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Available in a small HVQFN24 (4 × Applications Mobile phone Digital camera Personal digital assistant Digital video recorder 4. Ordering information Table 1. Ordering information Commercial product code Package description HVQFN24; 4 × 4 × 0.85 mm ...
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Block diagram V 3 SCL 2 SDA 1 ADR/PSW 5 INT_N 9 OE_N/INT_N 14 DAT/VP LEVEL 13 SHIFTER SE0/VM 12 RCV SPEED 8 SUSPEND 4 RESET_N exposed die pad DGND Fig 1. Block diagram ...
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Pinning information 6.1 Pinning Fig 2. Pin configuration HVQFN24 (top view) Fig 3. Pin configuration HVQFN24 (bottom view) ISP1301_5 Product data sheet terminal 1 index area ADR/PSW 1 SDA 2 SCL 3 ISP1301BS 4 RESET_N 5 INT_N SPEED 6 ...
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Pin description Table 2. [1] Symbol ADR/PSW SDA SCL RESET_N INT_N SPEED VREG3V3 SUSPEND OE_N/ INT_N VM VP RCV SE0/VM ISP1301_5 Product data sheet Pin description [2] Pin Type Reset Description state 1 I/O high-Z ADR input — sets ...
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Table 2. [1] Symbol DAT/ AGND ID V BUS CGND V CC(I/O) DGND [1] Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals. [ input output; ...
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Functional description 7.1 Serial controller The serial controller includes the following functions: • C-bus slave interface • Interrupt generator • Mode Control registers • OTG registers • Interrupt related registers • Device identification registers The serial controller ...
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ID detector In either active or suspended power mode, the ID detector senses the condition of the ID line and differentiates between the following three conditions: • Pin ID is floating; bit ID_FLOAT = 1 • Pin ID is ...
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Power-On Reset (POR) When will be typically 200 ns. The pulse is started when V PORP The POR function can be explained by viewing dips and the ...
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ISP1301BS Fig 5. Using external charge pump 7.10.2 SCL and SDA The SCL (serial clock) and SDA (serial data) signals implement a two-wire serial I 7.10.3 RESET_N Active LOW asynchronous reset for all digital logic. Either connect this pin to ...
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Bit TRANSP_EN = 0 • Bit UART_EN = 0 • Pin OE_N/INT_N = HIGH Table 12 shows the operation of the SE0/VM, DAT/VP and RCV pins during the receive operation. The VP and VM pins are single-ended receiver outputs ...
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Table 3. C ext 47 nF 100 nF [1] For output voltage V 7.10.12 V CC(I/O) This pin is an input and sets logic thresholds. It also powers the pads of the following logic pins: • ADR/PSW • DAT/VP, SE0/VM ...
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Direct direct I communicates with the serial controller through the SCL and SDA lines. The serial controller has a built- this mode, an external I (Status, Control, Interrupt, and so on) through the ...
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In UART mode, the OTG Controller is allowed to connect a UART to the DAT/VP and SE0/VM pins of the ISP1301. UART mode is entered by setting the UART_EN bit in the Mode Control 1 register. UART mode is equivalent ...
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Table 6. USB functional modes: I/O values [1] USB mode Bit DAT_SE0 VP_VM unidirectional 0 bidirectional 0 0 DAT_SE0 unidirectional 1 bidirectional 1 1 [1] Some of the modes and signals are provided to achieve backward compatibility with IP cores. ...
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Table 9. [1] Suspend [1] Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit. Table 10. USB mode DAT_SE0 VP_VM 9.2 Differential receiver Table 11 describes the operation of the differential ...
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Table 12. USB mode DAT_SE0 DAT_SE0 DAT_SE0 DAT_SE0 DAT_SE0 DAT_SE0 DAT_SE0 DAT_SE0 VP_VM VP_VM VP_VM VP_VM VP_VM VP_VM VP_VM VP_VM [1] Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit. ISP1301_5 Product data sheet USB functional ...
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Serial controller 10.1 Register map Table 13 provides an overview of the serial controller registers. Table 13. Serial controller registers Register Width Access (bits) Vendor Product Version Mode Control 1 ...
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Table 16. Version ID register: bit description Bit Symbol Access VERSIONID[15:0] R 10.1.2 Mode control registers 10.1.2.1 Mode Control 1 register (Set/Clear: 04h/05h) The bit allocation of the Mode Control 1 register is given in Table 17. ...
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Table 20. Bit Symbol 7 EN2V7 6 PSW_OE 5 AUDIO_EN TRANSP_BDIR[1:0] 2 BI_DI 1 SPD_SUSP_CTRL 0 GLOBAL_PWR_DN 10.1.3 OTG registers 10.1.3.1 OTG Control register (Set/Clear: 06h/07h) Table 21 provides the bit allocation of the OTG Control register. ...
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Table 22. Bit Symbol 2 DP_PULLDOWN 1 DM_PULLUP 0 DP_PULLUP 10.1.3.2 OTG Status register (Read: 10h) Table 23 shows the bit allocation of the OTG Status register. Table 23. OTG Status register: bit allocation Bit 7 6 Symbol B_SESS_ B_SESS_ ...
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Table 26. Bit Symbol 7 CR_INT 6 BDIS_ACON 5 ID_FLOAT 4 DM_HI 3 ID_GND 2 DP_HI 1 SESS_VLD 0 VBUS_VLD 10.1.4.2 Interrupt Latch register (Set/Clear: 0Ah/0Bh) This register indicates the source that generated the interrupt. The bit allocation of the ...
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Table 30. Bit Symbol 7 CR_INT 6 BDIS_ACON 5 ID_FLOAT 4 DM_HI 3 ID_GND 2 DP_HI 1 SESS_VLD 0 VBUS_VLD 10.1.4.4 Interrupt Enable High register (Set/Clear: 0Eh/0Fh) The Interrupt Enable High register enables interrupts on transition from FALSE to TRUE. ...
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The Interrupt Latch register bit is cleared by writing logic 1 to its clear address. 10.3 Auto-connect The Host Negotiation Protocol (HNP) in the OTG supplement specifies the following sequence of events to transfer the role of the host from ...
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Clock wake-up scheme The following subsections explain the ISP1301 clock stop timing, events triggering the clock to wake up, and the timing of the clock wake-up. 11.1 Power-down event The clock is stopped when the GLOBAL_PWR_DN bit is set. ...
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Fig 9. Clock wake- Fig 10. Clock wake- change (1) Fig 11. Clock wake- change (2) Fig 12. Clock wake-up by data line SRP When an event is triggered and the clock is started, ...
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I C-bus protocol For detailed information, refer to The I 2 12.1 I C-bus byte transfer format Table 33. [ Start. [ Acknowledge. [ Stop. 2 12.2 I C-bus device ...
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Table 36. Byte Write data K ACK P 12.3.2 Multiple-byte write Figure 13 Table 37. Byte S Device select ACK Register address K ACK Write data K ACK Write data ACK : Write data ...
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S device select S device select write data Fig 13. Writing data to the ISP1301 registers 12.4 Read format A read operation can be performed in two ways: • Current address read: to read the register at ...
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Fig 14. Current address read 12.4.2 Random address read 12.4.2.1 Single read Figure 15 Table 39. SDA line S Device select ACK Register address K ACK Device select ACK S Read data K No ACK P 12.4.2.2 Multiple read Figure ...
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Table 40. SDA line Read data − 1 slave transmits and master reads data register − 1. This is the last No ACK P ACK S device select wr ACK wr S device select ...
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Limiting values Table 41. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I I latch-up current lu V electrostatic discharge voltage ...
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Static characteristics Table 43. Static characteristics: supply pins CC(I/O) Symbol Parameter Charge pump disabled V output voltage from internal 3.3 V O(REG3V3) regulator ...
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Table 45. Static characteristics: analog I/O pins DP and CC(I/O) Symbol Parameter Input levels V differential input sensitivity DI V differential common-mode range ...
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Table 47. Static characteristics: charge pump CC(I/O) Symbol Parameter Current I load current load Voltage V output voltage on pin V O(VBUS) V leakage ...
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Dynamic characteristics Table 48. Dynamic characteristics: reset and clock CC(I/O) Symbol Parameter Reset t external RESET_N pulse width W(RESET_N) Internal clock f clock ...
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Table 50. Dynamic characteristics: analog I/O pins DP and CC(I/O) otherwise specified. Symbol Parameter t driver enable delay to HIGH PZH level t ...
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OE_N/INT_N DAT/VP SE0/VM Fig 20. SIE interface bus turnaround timing Load capacitance C Fig 21. Load on pins DP and for VREG3V3 for t Fig 22. Load on pins DP and DM ...
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Table 51. Characteristics of I/O stages of I Symbol Parameter f SCL clock frequency SCL t hold time for the START condition HD;STA t LOW period of the SCL clock (SCL)L t HIGH period of the SCL clock (SCL)H t ...
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V CC(I/O) V CC(I/ 100 3.3 3.3 10 kΩ 10 kΩ kΩ kΩ kΩ SDA SCL INT_N OTG CONTROLLER OE_N SE0 DAT C5 ...
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V CC(I/O) V CC(I/ 3.3 100 3.3 10 kΩ kΩ kΩ kΩ SDA SCL INT_N OTG CONTROLLER OE_N RCV 0.1 μF Fig 26. Application diagram ...
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Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS ...
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Abbreviations Table 52. Acronym ASIC ATX HNP ESD 2 I C-bus IC LSB OTG PDA PLD POR PORP SE0 SOF SRP USB USB-IF 20. References [1] ECN_27%_Resistor (Pull-up/pull-down Resistors ECN) [2] Universal Serial Bus Specification Rev. 2.0 [3] On-The-Go ...
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Revision history Table 53. Revision history Document ID Release date ISP1301_5 20090902 Modifications: Table 1 “Ordering ISP1301_4 20090624 ISP1301_3 20060221 ISP1301-02 20050104 (9397 750 14337) ISP1301-01 20040414 (9397 750 11355) ISP1301_5 Product data sheet Data sheet status Change notice ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . . . ...
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Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration HVQFN24 (top ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 24 Contents . . . . ...
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The contents of this document are subject to change without prior notice. ST-Ericsson makes no representation or warranty of any nature whatsoever (neither expressed nor implied) with respect to the matters addressed in this document, including but not limited to ...