SAA7105E/V1/G-T NXP Semiconductors, SAA7105E/V1/G-T Datasheet - Page 38
SAA7105E/V1/G-T
Manufacturer Part Number
SAA7105E/V1/G-T
Description
Video ICs PC-DENC
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7105EV1G-T.pdf
(70 pages)
Specifications of SAA7105E/V1/G-T
Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant
Other names
SAA7105E/V1/G,518
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Philips Semiconductors
Table 54 Logic levels and function of PHRES
Table 55 Logic levels and function of LDEL
Table 56 Logic levels and function of FLC
Table 57 Subaddress 6FH
Table 58 Logic levels and function of CCEN
2004 Mar 04
CCEN
TTXEN
SCCLN
PHRES1
Digital video encoder
CCEN1
LDEL1
BYTE
FLC1
DATA
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
PHRES0
CCEN0
LDEL0
LOGIC
LEVEL
FLC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
no subcarrier reset
subcarrier reset every two lines
subcarrier reset every eight fields
subcarrier reset every four fields
no luminance delay; default after reset
1 LLC luminance delay
2 LLC luminance delay
3 LLC luminance delay
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
enables individual line 21 encoding; see Table 58
disables teletext insertion; default after reset
enables teletext insertion
selects the actual line, where Closed Caption or extended data are encoded;
line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
line 21 encoding off; default after reset
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
38
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
SAA7104E; SAA7105E
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