P89V51RD2FA NXP Semiconductors, P89V51RD2FA Datasheet - Page 29
P89V51RD2FA
Manufacturer Part Number
P89V51RD2FA
Description
MCU 8-Bit 89V 80C51 CISC 64KB Flash 5V 44-Pin PLCC Tube
Manufacturer
NXP Semiconductors
Datasheet
1.P89V51RD2FA.pdf
(80 pages)
Specifications of P89V51RD2FA
Program Memory Size
64 KB
Package
44PLCC
Device Core
80C51
Family Name
89V
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
SPI/UART
Number Of Timers
3
Ram Size
1 KB
Program Memory Type
Flash
Operating Temperature
-40 to 85 °C
Controller Family/series
80C51
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
40MHz
No. Of Timers
4
No. Of Pwm Channels
5
Digital Ic Case Style
LCC
Core Size
8 Bit
Embedded Interface Type
UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
6.4.1 Mode 0
6.4.2 Mode 1
Table 18.
Putting either Timer into mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a fixed divide-by-32 prescaler.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the
Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer
to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a
control bit in the Special Function Register TCON
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Mode 1 is the same as mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See
Bit
2
1
0
Fig 8. Timer/counter 0 or 1 in mode 0 (13-bit counter)
INTn pin
TnGate
Tn pin
osc/6
TRn
TCON - Timer/counter control register (address 88H) bit description
Symbol
IT1
IE0
IT0
Figure
Rev. 05 — 12 November 2009
9.
C/T = 0
C/T = 1
Description
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 1.
Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 0.
control
P89V51RB2/RC2/RD2
Figure 8
8-bit microcontrollers with 80C51 core
(Figure
(5-bits)
TLn
shows mode 0 operation.
7). The GATE bit is in the TMOD
(8-bits)
THn
Figure
overflow
8). There are two
© NXP B.V. 2009. All rights reserved.
TFn
…continued
002aaa519
interrupt
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