P89V51RD2FA NXP Semiconductors, P89V51RD2FA Datasheet - Page 45

• Manufacturer Part Number: P89V51RD2FA
• Description: MCU 8-Bit 89V 80C51 CISC 64KB Flash 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P89V51RD2FA

• Program Memory Size: 64 KB
• Package: 44PLCC
• Device Core: 80C51
• Family Name: 89V
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Number Of Timers: 3
• Ram Size: 1 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Controller Family/series: 80C51
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 5
• Digital Ic Case Style: LCC
• Core Size: 8 Bit
• Embedded Interface Type: UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
Fig 19. SPI transfer format with CPHA = 1
Fig 20. Block diagram of programmable WDT
S PICL K (CPOL = 0)
S PICL K (CPOL = 1)
6.8 Watchdog timer
S PICL K cycle #
external reset
CLK (XTAL1)
(for reference)
(from master)
SS (to slave)
(from slave)
The device offers a programmable Watchdog Timer (WDT) for fail safe protection against
software deadlock and automatic recovery.
To protect the system against software deadlock, the user software must refresh the WDT
within a user-defined time period. If the software fails to do this periodical refresh, an
internal hardware reset will be initiated if enabled (WDRE = 1). The software can be
designed such that the WDT times out if the program does not work properly.
The WDT in the device uses the system clock (XTAL1) as its time base. So strictly
speaking, it is a Watchdog counter rather than a WDT. The WDT register will increment
every 344064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used
as the reload register of the WDT.
The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User
software can clear WDTS by writing ‘1' to it.
Figure 20
WDT operation. During Idle mode, WDT operation is temporarily suspended, and
resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
where WDTD is the value loaded into the WDTD register and f
frequency.
Period = (255
MOSI
MISO
WDTC
provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control
COUNTER
MSB
MSB
1
WDTD)
Rev. 05 — 12 November 2009
2
6
6
344064
clks
344064
3
5
5
UPPER BYTE
4
WDTD
WDT
4
4
1 / f
5
3
3
CLK(XTAL1)
P89V51RB2/RC2/RD2
WDT reset
6
2
2
8-bit microcontrollers with 80C51 core
7
1
1
LSB
002aaa531
8
internal reset
LSB
osc
is the oscillator
002aaa530
© NXP B.V. 2009. All rights reserved.
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