MT46H16M32LFCM-6:B Micron Technology Inc, MT46H16M32LFCM-6:B Datasheet
MT46H16M32LFCM-6:B
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MT46H16M32LFCM-6:B Summary of contents
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... PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN Products and specifications discussed herein are subject to change by Micron without notice. 512Mb: x16, x32 Mobile LPDDR SDRAM Options • DDQ – 1.8V/1.8V – 1.8V/1.2V • Configuration – 32 Meg Meg banks) – 16 Meg Meg banks) • ...
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... FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 16 Meg Meg banks 8K 8K ...
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... Rev. H, Production – 03/09 .......................................................................................................................... 96 Rev. G, Production – 02/09 .......................................................................................................................... 96 Rev. F, Production – 10/08 .......................................................................................................................... 96 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... Update – 05/08 ........................................................................................................................................... 97 Update – 03/08 ........................................................................................................................................... 98 Update – 12/07 ........................................................................................................................................... 98 Update – 07/07 ........................................................................................................................................... 98 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... Table 19: Truth Table – Current State Bank n – Command to Bank m .............................................................. 43 Table 20: Truth Table – CKE .......................................................................................................................... 46 Table 21: Burst Definition Table .................................................................................................................... 52 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... Figure 47: Bank Write – With Auto Precharge .................................................................................................. 87 Figure 48: Bank Write – Without Auto Precharge ............................................................................................. 88 Figure 49: Auto Refresh Mode ........................................................................................................................ 89 Figure 50: Self Refresh Mode ......................................................................................................................... 91 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM t t DQSQ, QH, and Data Valid Window (x16) ................................................... 68 t ...
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... Figure 52: Power-Down Mode (Active or Precharge) ....................................................................................... 93 Figure 53: Deep Power-Down Mode .............................................................................................................. 94 Figure 54: Clock Stop Mode ........................................................................................................................... 95 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... General Description The 512Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access mem- ory containing 536,870,912 bits internally configured as a quad-bank DRAM. Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8,192 rows by 512 columns by 32 bits. In the reduced page-size (LG) option, each of the x32’ ...
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... CAS# Refresh RAS# counter Standard mode register Extended mode register Address address BA0, BA1 register PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Bank 2 Bank 1 Bank 0 Row- address row- Bank 0 address Mux memory latch array and decoder ...
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... CS# logic WE# CAS# RAS# Standard mode register Extended mode register Address, Address BA0, BA1 register PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Bank 2 Bank 1 Refresh counter Bank 0 Row- row- address Bank 0 address MUX memory latch array and ...
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... Ball Assignments and Descriptions Figure 4: 60-Ball VFBGA – 8mm x 9mm (Top View test pin that must be tied to V Note: PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM DQ15 V SS SSQ V DQ13 DQ14 DDQ V DQ11 DQ12 SSQ V DQ9 ...
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... Figure 5: 90-Ball VFBGA – 10mm x 13mm and 9mm x 13mm (Top View test pin that must be tied to V Note: PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM DQ31 V SS SSQ V DQ29 DQ30 DDQ V DQ27 DQ28 SSQ V DQ25 DQ26 ...
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... LDQS, UDQS (60-ball) DQS[3:0] (90-ball) PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Type Description Input Clock the system clock input. CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK# ...
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... Table 3: VFBGA Ball Descriptions (Continued) Symbol DNU/A13 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Type Description V Supply DQ power supply. DDQ V Supply DQ ground. SSQ V Supply Power supply Supply Ground. SS – connect: May be left unconnected. Input Do not use. A13 if reduced page-size option is selected; other- wise, DNU ...
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... The pre-reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.6 7.2 0.8 TYP 0.8 TYP 1. All dimensions are in millimeters. Note: PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 0.65 ±0.05 0.3 ±0.025 8 ±0.1 Ball ±0. 4.5 ±0. ± ...
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... The pre-reflow balls are Ø0.42 on Ø0 SMD ball pads. 5.6 11.2 0.8 TYP 3.2 1. All dimensions are in millimeters. Note: PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 0.65 ±0.05 10 ±0.1 Ball ±0. 6.5 ±0. ...
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... Solder ball material: SAC105. Dimensions apply to solder balls post reflow on Ø0.4 SMD ball pads. 11.2 CTR 0.8 TYP 1. All dimensions are in millimeters. Note: PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 0.65 ±0.1 Ball ±0 ...
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... DC output high voltage: Logic output low voltage: Logic Leakage current Input leakage current Any input 0V ≤ V ≤ (All other pins not under test = 0V) PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Symbol DDQ STG and V must be within 300mV of each other at all times. V ...
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... Output leakage current (DQ are disabled; 0V ≤ V ≤ V OUT DDQ Operating temperature Commercial Industrial Notes: 1. All voltages referenced All parameters assume proper device initialization. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM /V = 1.70–1.95V DD DDQ Symbol 1.70– ...
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... The input capacitance per pin group will not differ by more than this maximum amount PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM , and electrical AC and DC characteristics may be conducted at DD nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified ...
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... The I/O capacitance per DQS and DQ byte/group will not differ by more than this maxi- PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM mum amount for any given device. 21 Electrical Specifications Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... Data bus inputs are stable Deep power-down current: Address and control balls are stable; Data bus inputs are stable PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – I Parameters 1.70–1.95V ...
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... Data bus inputs are stable Deep power-down current: Address and control pins are stable; Data bus inputs are stable PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – 1.70–1.95V DD DDQ ...
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... This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH 12. Values for I 13. Typical values at 25˚C, not a maximum value. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – I Full array, 85˚C Full array, 45˚C 1/2 array, 85˚C 1/2 array, 45˚ ...
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... PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – 100 105 Temperature (°C) 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... DQS falling edge from CK rising – hold time DQS falling edge to CK rising – setup time Data valid output window PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – AC Operating Conditions /V = 1.70–1.95V DD DDQ -5 -54 ...
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... Average periodic refresh interval AUTO REFRESH command period PRECHARGE command period DQS read preamble DQS read preamble PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – AC Operating Conditions /V = 1.70–1.95V DD DDQ -5 -54 Symbol Min Max Min t t – ...
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... The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point and CK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for 7. All AC timings assume an input slew rate of 1 V/ns. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – AC Operating Conditions /V = 1.70–1.95V DD ...
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... At least 1 clock cycle is required during 27. Clock must be toggled a minimum of two times during the PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – AC Operating Conditions clock at which the READ command was registered; for the first data element valid at (2 × ...
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... Based on nominal impedance of 25Ω (full strength Notes: 2. The full variation in driver current from minimum to maximum, due to process, voltage, PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 2.80 18.53 5 ...
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... Based on nominal impedance of 37Ω (three-quarter drive strength Notes: 2. The full variation in driver current from minimum to maximum, due to process, voltage, 3. Contact factory for availability of three-quarter drive strength. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 1 ...
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... Based on nominal impedance of 37Ω (three-quarter drive strength Notes: 2. The full variation in driver current from minimum to maximum, due to process, voltage, 3. Contact factory for availability of three-quarter drive strength. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 1 ...
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... Notes: 2. The full variation in driver current from minimum to maximum, due to process, voltage, 3. The I-V curve for one-quarter drive strength is approximately 50% of one-half drive PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Pull-Down Current (mA) Min Max 0.00 0.00 1 ...
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... Functional Description The Mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O. Single read or write access for the device consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock- cycle data transfers at the I/O ...
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... This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 8. Internal refresh counter controls row addressing; in self refresh mode all inputs and I/Os 9. BA0–BA1 select the standard mode register, extended mode register, or status register. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM CS ...
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... A[0:n] selects the row. This row remains active for accesses until a PRE- CHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Valid ...
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... READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE HIGH ...
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... If a WRITE or a READ is in progress, the entire data burst must be complete prior to stopping the clock (see Clock Change Frequency (page 95)). A burst completion for WRITEs is defined when the write postamble and PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE HIGH ...
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... BA0 and BA1 select the bank. Otherwise, BA0 and BA1 are treated as “Don’t Care.” After a bank has been precharged the idle state and must be activa- ted prior to any READ or WRITE commands being issued to that bank. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE HIGH ...
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... AUTO REFRESH AUTO REFRESH is used during normal operation of the device and is analogous to CAS#- BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is required. Addressing is generated by the internal refresh controller. This makes the address bits a “ ...
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... BURST TERMINATE command with CKE LOW. Figure 14: DEEP POWER-DOWN Command RAS# CAS# Address BA0, BA1 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE CS# WE# Don’t Care 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... This table is bank-specific, except where noted (for example, the current state is for a 3. Current state definitions: 4. The states listed below must not be interrupted by a command issued to the same bank. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM CAS# WE# Command/Action X X ...
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... L L PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Read with auto-precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when be in the idle state. Write with auto-precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when will be in the idle state ...
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... This table applies when CKE Notes: 2. This table describes alternate bank operation, except where noted (for example, the cur- 3. Current state definitions: PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM CAS# WE# Command/Action H H ACTIVE (select and activate row) ...
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... All states and sequences not shown are illegal or reserved. 6. Requires appropriate DM masking WRITE command can be applied after the completion of the READ burst; otherwise, a PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM From Command To Command READ with READ or READ with auto precharge ...
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... CKE Notes: 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMAND 4. All states and sequences not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on each clock edge occurring during the 6. After exiting deep power-down mode, a full DRAM initialization sequence is required. ...
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... WRITE A PRE ACT = ACTIVE AREF = AUTO REFRESH BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down DPD = Enter deep power-down PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Self refresh DPDX Deep SREFX power- down SREF DPD ...
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... Issue NOP or DESELECT commands for at least After steps 1–10 are completed, the device has been properly initialized and is ready to receive any valid command. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM ) and I/O power ( recommended that V and V ...
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... PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command AUTO RE- 2. NOP or DESELECT commands are required for at least 200μs. 3. Other valid commands are possible. 4. NOPs or DESELECTs are required during this time. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 Ta0 ...
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... CK stable DD 1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command AUTO RE- Notes: 2. NOP or DESELECT commands are required for at least 200μs. 3. Other valid commands are possible. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T0 Ta0 ( ( ( ( ...
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... Note: Burst Length Read and write accesses to the device are burst-oriented, and the burst length (BL) is programmable. The burst length determines the maximum number of column loca- PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM BA1 BA0 An ... A10 A9 ...
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... The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Table 21: Burst Definition Table Burst Length Starting Column Address PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Order of Accesses Within a Burst Type = Sequential A0 0 0 0-1-2 1-2-3 2-3-0 3-0-1-2 A1 ...
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... For the READ command is registered at clock edge n, then the data will be nominally available clocks + tered at clock edge n, then the data will be nominally available clock + PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Order of Accesses Within a Burst Type = Sequential 0 0 ...
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... A[n:7] each set to zero, and bits A[6:0] set to the desired values. All other combinations of values for A[n:7] are reserved for future use. Reserved states should not be used because unknown operation or incompatibility with future versions may result. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T0 T1 T1n CK# CK ...
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... Programming the temperature-compensated self refresh (TCSR) bits will have no effect on the device. The self refresh oscillator will continue to refresh at the optimal factory-programmed rate for the device temperature. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM BA0 An ... A10 ...
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... The output driver settings are 25Ω, 37Ω, and 55Ω internal impedance for full, three-quarter, and one-half drive strengths, respectively. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM Extended Mode Register 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register. 5. The second bit of the data-out burst is a “Don’t Care.” PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM set SRR; only NOP or DESELECT commands are supported during the mand is issued ...
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... Reserved Notes: 1. Reserved bits should be set to 0 for future compatibility. 2. Refresh multiplier is based on the memory device on-board temperature sensor. Re- PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 S12 S11 ...
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... The mini- mum time interval between successive ACTIVE commands to different banks is defined t by RRD. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM t RCD specification. 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. Bank/Row Activation t RC. © ...
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... READ command, where x equals the number of desired data element pairs. This is shown in Figure 29 (page 67). Following the PRECHARGE command, a subsequent PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM t DQSQ (valid data-out skew), t DQSCK (DQS transition skew to CK) and 60 Micron Technology, Inc ...
Page 61
... Address Bank a, Col n DQS DQ T0 CK# CK Command READ Address Bank a, Col n DQS Notes Shown with nominal PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n NOP NOP OUT OUT T1 T2 T2n NOP NOP data-out from column n. ...
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... D Notes (if 4, the bursts are concatenated 16, the second burst interrupts 3. Shown with nominal 4. Example applies only when READ commands are issued to same device. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n NOP READ Bank, ...
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... Col n DQS Notes (if burst 16, the second burst interrupts the first). 3. Shown with nominal 4. Example applies when READ commands are issued to different devices or nonconsecu- PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP READ Bank, ...
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... Bank, Address Col n DQS Notes ( 16, the following burst interrupts the previous). 3. READs are to an active row in any bank. 4. Shown with nominal PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n READ READ Bank, Bank, Col x Col ...
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... CK Command 1 READ Bank a, Address Col n DQS 16. Notes: 2. BST = BURST TERMINATE command; page remains open Shown with nominal 5. CKE = HIGH. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 2 BST NOP OUT OUT T1 T2 T2n 2 BST NOP ...
Page 66
... the cases shown (applies for bursts of 8 and 16 as well the BST com- Notes: 2. BST = BURST TERMINATE command; page remains open Shown with nominal 6. CKE = HIGH. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 2 BST NOP ...
Page 67
... PRE = PRECHARGE command. 3. ACT = ACTIVE command Shown with nominal 6. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out READ command with auto precharge enabled, provided PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 2 NOP PRE Bank a, ...
Page 68
... DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7 The data valid window is derived for each DQS transitions and is defined as 7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM t t DQSQ, QH, and Data Valid Window (x16) T1 ...
Page 69
... The data valid window is derived for each DQS transition and is 7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM t t DQSQ, QH, and Data Valid Window (x32) ...
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... NOP DQS or LDQS/UDQS 2 All DQ values, collectively 3 1. Commands other than NOP can be valid during this cycle. Notes transitioning after DQS transitions define 3. All DQ must transition by 4. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM and DQSCK T2n ...
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... Data for any WRITE burst can be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, Figure 42 (page 80). PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM DQSS [MAX]) might not be obvious, they have also been included. Figure 35 71 Micron Technology, Inc ...
Page 72
... For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0 con- 5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 con- PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM t WR period are written to the internal array, and 1 ...
Page 73
... DM 1. NOP commands are shown for ease of illustration; other commands may be valid at Notes the case shown. 3. PRE = PRECHARGE. 4. Disable auto precharge. 5. Bank “Don’t Care” if A10 is HIGH at T8 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM ...
Page 74
... DQSS (NOM) t DQSS (MIN) t DQSS (MAX uninterrupted burst shown. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T0 T1 CK# CK 1,2 WRITE NOP Bank a, Col b t DQSS DQS ...
Page 75
... Command 1,2 WRITE Bank, Address Col b t DQSS (NOM) DQS Each WRITE command can be to any bank. Notes uninterrupted burst shown PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 1, 2 NOP WRITE Bank, Col (n) = data-in for column b (n). ...
Page 76
... DQSS (NOM) DQS DQ 3,4 DM Notes: 1. Each WRITE command can be to any bank. 2. Programmed cases shown ( the next data-in following D PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 1,2 1,2 WRITE WRITE Bank, Bank, Col x Col n ...
Page 77
... The READ and WRITE commands are to the same device. However, the READ and WRITE Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled uninterrupted burst shown PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
Page 78
... An interrupted burst shown; 2 data elements are written. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled DQS is required at T2 and T2n (nominal case) to register DM PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
Page 79
... An interrupted burst shown; 1 data element is written, 3 are masked. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled DQS is required at T2 and T2n (nominal case) to register DM PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
Page 80
... An uninterrupted burst shown. 2. A10 is LOW with the WRITE command (auto precharge is disabled). 3. PRE = PRECHARGE. 4. The PRECHARGE and WRITE commands are to the same device. However, the PRE PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
Page 81
... An interrupted burst shown; two data elements are written. Notes: 2. A10 is LOW with the WRITE command (auto precharge is disabled). 3. PRE = PRECHARGE DQS is required at T4 and T4n to register DM PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP NOP ...
Page 82
... A10 is LOW with the WRITE command (auto precharge is disabled). 3. PRE = PRECHARGE DQS is required at T4 and T4n to register DM burst used, DQS and DM are not required at T3, T3n, T4, and T4n PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n T3 NOP NOP ...
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... Figure 46 (page 86). Bank WRITE operations with and without auto precharge are shown in Figure 47 (page 87) and Figure 48 (page 88). PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM t RP) after the PRECHARGE command is issued. Input A10 deter (the precharge period) begins. For READ with auto pre- ...
Page 84
... In either situation, all other related limitations apply (for example, contention between READ data and WRITE data must be avoided). PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. Auto Precharge ...
Page 85
... NOP commands are shown for ease of illustration; other commands may be valid at Notes the case shown. 3. Enable auto precharge. 4. Refer to Figure 30 (page 68) and Figure 31 (page 69) for detailed DQS and DQ timing PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM ...
Page 86
... PRE = PRECHARGE. 4. Disable auto precharge. 5. Bank “Don’t Care” if A10 is HIGH at T5. 6. The PRECHARGE command can only be applied Refer to Figure 30 (page 68) and Figure 31 (page 69) for DQS and DQ timing details PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM ...
Page 87
... A10 Row BA0, BA1 Bank x DQS NOP commands are shown for ease of illustration; other commands may be valid at Notes the case shown. 3. Enable auto precharge PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM NOP WRITE NOP Col n Note ...
Page 88
... DQ DM Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid the case shown. 3. PRE = PRECHARGE. 4. Disable auto precharge. 5. Bank “Don’t Care” if A10 is HIGH at T8 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM ...
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... AUTO REFRESH Operation Auto refresh mode is used during normal operation of the device and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH com- mand is nonpersistent and must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “ ...
Page 90
... SELF REFRESH command must not be used as a substitute for the AUTO REFRESH command. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM t XSR to complete any internal refresh already in progress. 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 91
... CKE is registered HIGH (in conjunction with a NOP or DESELECT command). NOP or DESELECT commands must be maintained on the command bus until satisfied. See Figure 52 (page 93) for a detailed illustration of power-down mode. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM T1 Ta0 ( ( ) ...
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... Figure 51: Power-Down Entry (in Active or Precharge Mode) RAS#, CAS#, WE# RAS#, CAS#, WE# PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE CS# Or CS# Address BA0, BA1 Don’t Care 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 93
... LOW to maintain DPD mode. The clock must be stable prior to exiting DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT com- mand present on the command bus. After exiting DPD mode, a full DRAM initialization sequence is required. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – ...
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... All banks idle with no activity on the data bus 1. Clock must be stable prior to CKE going HIGH. Notes: 2. DPD = deep power-down. 3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required. PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 1 ...
Page 95
... The device enables the clock to change frequency during operation only if all timing parameters are met and all refresh requirements are satisfied. The clock can be stopped altogether if there are no DRAM operations in progress that would be affected by this change. Any DRAM operation already in process must be com- pleted before entering clock stop mode ...
Page 96
... Table 11: “Electrical Characteristics and Recommended AC Operating Conditions:” – Changed the following specification: tRC -75 to 67.5ns – Removed note 21 PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM t RFC values from 97.5ns to 72ns in Table 11 (page 26). t CKE symbol in Table 11 (page 26). ...
Page 97
... Added “L” low-power option to Figure 1: “512Mb Mobile DDR Part Numbering” and Table 9: “Idd6 Specifications and Conditions” PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. Revision History ...
Page 98
... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- PDF: 09005aef82d5d305 512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN 512Mb: x16, x32 Mobile LPDDR SDRAM times occur. 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...