MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 106

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Figure 46:
Write Leveling Mode Exit Procedure
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
Early remaining DQ
Late remaining DQ
Differential DQS 4
Prime DQ 5
Command
ODT
CK#
CK
Write Leveling Sequence
MRS 1
Notes:
t MOD
NOP 2
1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or DES.
3. DQS, DQS# needs to fulfill minimum pulse width requirements
4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the
5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are
After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 47 on page 107 depicts a general procedure in exiting write
leveling mode. After the last rising DQS (capturing a “1” at T0), the memory controller
should stop driving the DQS signals after
the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls
become undefined when DQS no longer remains LOW, and they remain undefined until
t
The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the
DQS is no longer driving LOW. When ODT LOW satisfies
~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After
command may be registered by the DRAM. Some MRS commands may be issued after
t
MOD after the MRS command (at Te1).
MRD (at Td1).
t WLDQSEN
t
zero crossings. The solid line represents DQS; the dotted line represents DQS#.
driven LOW and remain in this state throughout the leveling procedure.
DQSL (MIN) as defined for regular writes. The maximum pulse width is system-dependent.
NOP
t WLMRD
NOP
t DQSL 3
NOP
t WLH
106
T1
NOP
Indicates a Break in
Time Scale
t WLO
t WLO
t WLO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
t
WLO (MAX) delay plus enough delay to enable
t DQSL 3
t
MOD is satisfied (at Te1), any valid
NOP
2Gb: x4, x8, x16 DDR3 SDRAM
t WLS
Undefined Driving Mode
NOP
t
T2
IS, ODT must be kept LOW (at
t DQSH 3
t
©2006 Micron Technology, Inc. All rights reserved.
DQSH (MIN) and
NOP
t WLO
NOP
Commands
Don’t Care
NOP